Scaling and carrier transport behavior of buried-channel In0.7Ga0.3As MOSFETs with Al2O3 insulator

Solid-State Electronics 111 (2015) 218–222

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Scaling and carrier transport behavior of buried-channel In0.7Ga0.3As MOSFETs with Al2O3 insulator Taewoo Kim a, Dae-Hyun Kim b,⇑ a b

SEMATECH, Albany, New York 12203, USA School of Electronics Engineering, Kyungpook National University, Republic of Korea

a r t i c l e

i n f o

Article history: Received 12 March 2015 Received in revised form 9 May 2015 Accepted 29 May 2015 Available online 30 June 2015 Keywords: InGaAs MOSFETs Logic Buried-channel Interfacial-state density

a b s t r a c t In this paper, we investigate the scaling and carrier transport behavior of sub-100 nm In0.7Ga0.3As buried-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with Al2O3 as gate dielectric. The device combines a 3-nm Al2O3 layer grown by atomic-layer-deposition (ALD) and a 13-nm In0.52Al0.48As insulator grown by molecular-beam-epitaxy (MBE). Our long channel device with Lg = 200 nm exhibits excellent subthreshold characteristics, such as subthreshold-swing (S) of 68 mV/decade at VDS = 0.5 V, indicating a very good interface quality between Al2O3 and In0.52Al0.48As. In addition, a short-channel device with Lg = 60 nm maintains electrostatic integrity of the device, such as subthreshold-swing (S) = 90 mV/decade and drain-induced-barrier-lowering (DIBL) = 100 mV/V at VDS = 0.5 V. We show well-behaved electrostatic scaling behavior that follows a modified FD-SOI MOSFET model. Our experimental and theoretical research suggest that further device optimization in the form of a self-aligned contact structure and aggressive EOT scaling would lead to high-performance III–V MOSFETs for multiple types of applications. Ó 2015 The Authors. Published by Elsevier Ltd. This is an open access article under the CC BY license (http:// creativecommons.org/licenses/by/4.0/).

1. Introduction Scaling of transistor footprint has been the top priority in the semiconductor industry for several decades. Transistor size scaling leads to increasing transistor density (Moore’s law). While a matter of considerable debate, the semiconductor device technology that has been a cornerstone of the micro-electronic revolution of the last four decades appears to be reaching the end of its roadmap. There are severe doubts that it will make economic sense for Si c omplementary-metal-oxide-semiconductor (CMOS) transistors to scale beyond sub-10-nm channel lengths. At its heart, the problem is the increasing difficulty in maintaining performance out of deeply scaled Si CMOS when the operating voltage is reduced. This is required in order to maintain power density within economical goal. In the landscape of alternatives to Si CMOS for next-generation logic applications, III–V compound semiconductors have recently emerged as a viable option, not only because of their superior electron transport properties [1, references therein] but also because of the existence of a mature and reliable III–V transistor technology that has been extensively used in many commercial and defense applications for the past three decades. Among the III–V compound ⇑ Corresponding author. E-mail address: [email protected] (D.-H. Kim).

semiconductors, InAs-rich InxGa1xAs (x > 0.53) has received a great deal of interest as a strong candidate for high-performance (HP) logic applications [2,3]. Recent studies on high-electron-mobility transistors (HEMTs), which constitute an excellent test vehicle to investigate issues of relevance to future III–V CMOS, have clearly demonstrated excellent logic characteristics and scalability down to Lg = 30 nm regime, in the form of on-current (ION), subthresholdswing (S), drain-induced-barrier-lowering (DIBL), logic gate-delay (CV/I) and switching energy [4]. Recent strong interest in this area has brought about significant progress on gate dielectric integration, transistor architecture, and process integration in InGaAs MOSFETs. Especially, a high quality dielectric/channel interface has been successfully demonstrated in III–V MOSFETs by a number of different groups around the world [5–16]. In order to maximize ION/IOFF ratio, a steep subthreshold behavior is critical, together with excellent short-channel effects and gate length (Lg) scalability. However, this inevitably requires the formation of an extremely high quality dielectric–semiconduc tor interface to lower the interface-state-density (Dit) near the conduction-band edge. This has been proven difficult in a surface channel approach where interface roughness scattering degrades carrier transport properties [17]. To address this, a buried-channel InGaAs MOSFET is being explored as an alternative, that aims to mitigate the pressure of the low Dit requirement and interface roughness scattering [13,15,18].

http://dx.doi.org/10.1016/j.sse.2015.05.040 0038-1101/Ó 2015 The Authors. Published by Elsevier Ltd. This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/).

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Gate (Ti/Au)

S

D Oxide

Cap Etch stopper Barrier

Al2O3

Channel Buffer

Fig. 1. Schematic of recessed Quantum-well (QW) buried-channel In0.7Ga0.3As MOSFETs with 3-nm Al2O3 by ALD on top of MBE-grown In0.52Al0.48As barrier.

In this paper, we report sub-100 nm recessed buried-channel In0.7Ga0.3As MOSFETs that uses a combination of ALD Al2O3 and MBE In0.52Al0.48As as a composite barrier. The outstanding subthreshold and scaling characteristics that are obtained down to Lg = 60 nm bodes well for the future of III–V logic MOSFETs based on this material system. 2. Process technology Fig. 1 shows the cross section of the devices fabricated in this work. The epitaxial heterostructure is grown by molecular beam epitaxy (MBE) on a 100-mm semi-insulating InP substrate. In essence, this is an InAlAs/InGaAs HEMT structure [2] that, from top to bottom, consists of a heavily doped multi-layer cap

(In0.7Ga0.3As with 5  1019/cm3, In0.53Ga0.47As 5  1019/cm3 and In0.52Al0.48As with 1  1019/cm3), 4-nm InP etch-stopper, 10-nm In0.52Al0.48As barrier, Si d-doping, 3-nm In0.52Al0.48As spacer, 10-nm In0.7Ga0.3As channel and 300-nm In0.52Al0.48As buffer on an InP substrate. In a Hall epi wafer which has the same structure as the device wafer but otherwise uses a simpler 4 nm In0.53Ga0.47As cap with a Si doping density of 1  1018 cm3, the Hall mobility (ln,Hall) and 2-DEG sheet carrier concentration (ns) were measured to be around 11,000 cm2/V s and 3  1012/cm2 at room temperature. Device fabrication took place broadly the same lines of conventional HEMTs [2], except for the deposition of a gate insulator prior to gate metal formation. Fig. 2 illustrates some of the key process steps. It begins with mesa isolation. Then, non-alloyed Mo/Ti/Pt/Au (10/10/10/150 nm) source and drain ohmic contacts with a 2 lm spacing are patterned, evaporated and lifted off. This is followed by 20-nm SiO2 deposition by plasma-enhanced-chem ical-vapor-deposition (PECVD). A fine gate pattern using single-layer ZEP-520A is defined by e-beam lithography. This is then transferred to the passivating SiO2 layer by CF4 plasma. Following this, the multi-layer cap is etched isotropically using a mixture of citric acid and hydrogen-per-oxide (H2O2) with 20:1 volume ratio. After removal of the ZEP-520A e-beam resist, the InP layer is selectively etched in an anisotropic fashion by low-damage Ar-plasma against the In0.52Al0.48As barrier [19]. Immediately, 3 nm of Al2O3 is deposited by ALD at 250 °C. A second e-beam lithography is carried out to define a dielectric-assisted T-gate [20]. Ti/Au gate metal is evaporated and lifted off. Finally, a post-metal annealing (PMA) is performed under N2 ambient at 350 °C for 1 min. In this way, devices with Lg from 200 nm to 60 nm have been fabricated. Fig. 3 shows TEM images of the cross section of a typical Lg = 60 nm device. No evidence of residual surface oxides at the Al2O3/In0.52Al0.48As interface is visible. 3. Results and discussion First, we investigate the gate length (Lg) scaling behavior of the logic characteristics of devices in more detail. The benefit from Lg

ZEP S

Cap

Ar Plasma SiO2

D Drain

Drain

Insulator

InP

Channel Buffer (a) Selective Wet Etch: Cap

(b) Selective Ar RIE: InP

Drain

Al2O3

(c) Al2O3 deposition by ALD Fig. 2. Some of key steps to form Al2O3/In0.52Al0.48As composite insulators in this work.

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(a)

(b)

Fig. 3. TEM images of a fabricated device: (a) physical gate length (Lg) is 60 nm, and (b) Al2O3 is 3 nm and In0.52Al0.48As is 13 nm, respectively.

1.2

-0.1

Lg = 200 nm Lg = 100 nm Lg = 60 nm

VDS = 0.05 V VDS = 0.5 V

VDS = 0.5 V -0.2

VT [V]

gm [mS/μm]

0.8 -0.3

0.4 -0.4

0.0 -0.50

-0.25

0.00

0.25

0.50

Fig. 4. Transconductance (gm) characteristics of In0.7Ga0.3As buried-channel MOSFETs at VDS = 0.5 V for three different gate lengths of 200 nm, 100 nm and 60 nm.

scaling can be qualitatively observed in the transconductance (gm) characteristics. Fig. 4 shows the measured gm as a function of VGS for In0.7Ga0.3As buried-channel MOSFETs with three different

10-3

VDS = 0.5 V VDS = 0.05 V

ID [A/μm]

10-5 10-6 10-7 10-8

Lg = 60 nm Lg = 100 nm Lg = 200 nm

10-9 10-10 -0.75

-0.50

-0.25

0.00

0

50

100

150

200

250

Lg [nm]

VGS [V]

10-4

-0.5

0.25

0.50

VGS [V] Fig. 5. Subthreshold characteristics of In0.7Ga0.3As buried-channel MOSFETs with 350 °C PDA for three different values of Lg, at VDS = 0.05 V and 0.5 V.

Fig. 6. VT roll-off behavior of our In0.7Ga0.3As buried-channel MOSFETs at VDS = 0.05 V and 0.5 V.

values of Lg (60, 100 and 200 nm), at VDS = 0.5 V. The peak gm increases prominently down to Lg = 100 nm but saturates beyond this point. This is very similar to what we have seen from III–V HEMTs with similar values of equivalent-oxide-thickness (EOT) [2]. A significant improvement in gm scaling would be possible using a thinner insulator design scheme [2]. Fig. 5 shows the subthreshold characteristics of In0.7Ga0.3As buried-channel MOSFETs for three different values of Lg, at VDS = 0.05 V and 0.5 V. First of all, the device with Lg = 200 nm exhibits excellent subthreshold characteristics, such as S = 68 mV/dec., and DIBL = 25 mV/V at VDS = 0.5 V. As Lg decreases, the subthreshold characteristics soften and there is a negative shift of VT with VDS. Fig. 6 shows VT roll-off behavior for the same devices at VDS = 0.05 V and 0.5 V. The devices in this work exhibit VT roll-off of about 70 mV at VDS = 0.5 V, as Lg scales down to 60 nm. We have compared the logic figures of merit of our devices with those of III–V MOSFETs published in the literature. Fig. 7(a) and (b) plots DIBL and subthreshold-swing as a function of Lg for our recessed Quantum-Well MOSFETs with composite insulator to prior reports on III–V MOSFETs with planar gate architecture. Clearly, the devices in this work exhibit the best DIBL and S in the sub-100 nm regime of all III–V MOSFETs despite the relatively high value of EOT. To theoretically understand the scaling potential of our recessed InGaAs MOSFETs, we have used a scaling model originally

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DIBL[mV/V]

400

300

This work Buried-channel [18], VDS = 0.5 V [5], VDS = 0.5 V [9], VDS = 0.5 V Surface-channel [13], VDS = 1 V [16], VDS = 0.5 V

200

250

Yan's model [21] InGaAs MOSFETs (This work)

200

DIBL [mV/V]

(a) 500

150

100

50 100

0

VDS = 0.5 V

S [mV/dec.]

300

This work Buried-channel [18], VDS = 0.5 V [5], VDS = 0.5 V [9], VDS = 0.5 V Surface-channel [13], VDS = 1 V [16], VDS = 0.5 V

200

100

5

10

15

20

Scaling parameter (γ) Fig. 8. DIBL against scaling parameter (k) for our recessed In0.7Ga0.3As MOSFETs with composite insulator (this work), and FD-SOI model [21].

FD-SOI model [21]. The universal relationship between DIBL and aspect ratio proves the excellent scaling behavior of our recessed MOS-HEMTs and constitutes an effective guideline for future device design. A striking aspect of our recessed InGaAs MOSFETs is their outstanding subthreshold and short-channel effects down to Lg = 60 nm. This is in spite of the relatively thick EOT. This suggests a very small interface state density (Dit) below the conduction band edge. We have estimated the effective Dit from the DC subthreshold-swing of long channel devices, as follows:

S  ðkT=qÞðln 10Þ  ð1 þ qDit =C ox Þ

VDS = 0.5 V 0

VDS = 0.5 V 0

100

L g [nm]

(b) 400

0

100

Lg [nm] Fig. 7. Benchmarking against reported III–V MOSFETs with planar architecture: (a) Drain-Induced-Barrier-Lowering (DIBL) vs. Lg and (b) Subthreshold-swing (S) vs. Lg.

developed for the electrostatics of fully-depleted (FD) SOI MOSFETs [21]. From an electrostatic point of view, these two types of devices behave in a similar way. The bottom In0.52Al0.48As back-barrier/buffer plays the same role as buried oxide (Box). The In0.7Ga0.3As quantum-well channel mimics the thin Si-body and the Al2O3/In0.52Al0.48As composite insulator acts as the gate oxide. In this model, there is a key length scale (k) that is given by the permittivity of the insulator and channel materials, and the thickness of each layer:

rffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi er;ch ; k ¼ t0ins t ch

er;ins

In these equations, tch and er,ch are the thickness and permittivity of the channel layer, respectively. tins0 corresponds to the effective insulator thickness, which is weighted by respective dielectric constant of Al2O3, In0.52Al0.48As and half of In0.7Ga0.3As channel. The reason for half of the channel is to consider the quantum nature of the electron distribution in the InGaAs well. This is also described by the so-called ‘centroid’ capacitance (Ccentroid) [22]. er,ins0 is the effective permittivity of the total barrier that adequately weight the relative contribution of Al2O3, In0.52Al0.48As and In0.7Ga0.3As layers according to their respective thickness and permittivity. In the model of [21] for FD-SOI MOSFETs, the short-channel effects are set by the aspect ratio (or scaling parameter) (k = Lg/k). Fig. 8 shows the dependence of DIBL on the aspect ratio c for our recessed MOSFETs, together with the

Here, Cox is only due to the Al2O3 and can be calculated from dielectric constant and physical thickness. From S = 68 mV/decade in our MOSFET with Lg = 200 nm, Dit as low as 3  1012/cm2 eV is obtained. This reveals that the buried channel architecture is an effective remedy to mitigate the pressure of Dit engineering and is very promising for future III–V MOSFETs. Nevertheless, it is still of critical importance to minimize a value of Dit itself, to prevent the channel carrier transport from being degraded. Kim et al. successfully reported benefits of using a H2 forming-gas-anneal (FGA) in passivating the InGaAs surface/interface with dielectrics, leading to the considerable improvement in Dit [23]. Combined with post-metal-annealing (PMA) in the context of FGA, the buried-channel design scheme would significantly improve the logic and high-speed characteristics of future indium-rich InxGa1xAs MOSFETs. 4. Conclusion In summary, we have demonstrated sub-100 nm recessed buried-channel Quantum-Well In0.7Ga0.3As MOSFETs with Al2O3 as gate dielectric. Our devices exhibit outstanding logic characteristics and scalability with DIBL = 100 mV/V and S = 90 mV/decade, at Lg = 60 nm. In spite of the relatively thick EOT and RSD, our device shows gm in excess of 1000 lS/lm. In addition, a long channel device with Lg = 200 nm displays a sharp subthreshold behavior of S = 68 mV/decade at VDS = 0.5 V. Finally, we have estimated Dit = 3  1012/cm2 eV from the DC subthreshold characteristics of the long-channel devices. Acknowledgement This work was supported by the BK21 Plus Project through the Ministry of Education, Korea, under Grant 21A20131600011, and by a grant from the R&D Program for Industrial Core Technology

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funded by the Ministry of Trade, Industry and Energy, Republic of Korea (Grant No. 10045216). References [1] del Alamo JA. Nanometre-scale electronics with III–V compound semiconductors. Nature 2011;479:317–23. [2] Kim D-H, del Alamo JA. Lateral and vertical scaling of In0.7Ga0.3As HEMTs for post-Si-CMOS logic applications. IEEE Trans Electron Dev 2008;55(10):2546–53. [3] Kim DH, del Alamo JA, Antoniadis DA, Brar B. Extraction of virtual-source injection velocity in sub-100 nm III–V HFETs. In: Int Electron Devices Meeting (IEDM) Tech Dig; 2009. p. 861–4. [4] del Alamo JA, Kim DH, Kim TW, Jin D, Antoniadis DA. III–V CMOS: What have we learned from HEMTs? In: The 23rd IEEE indium phosphide and related materials conference (IPRM); May 2011. [5] Radosavljevic M, Chu-Kung B, Corcoran S, Dewey G, Hudait MK, Fastenau JM, et al. Advanced high-k gate dielectric for high-performance short-channel In0.7Ga0.3As quantum well field effect transistors on silicon for low power logic applications. Int Electron Devi Meeting (IEDM) Tech Dig 2009:319–22. [6] Radosavljevic M, Chu-Kung B, Corcoran S, Dewey G, Hudait MK, Fastenau JM, et al. Non-planar, multi-gate InGaAs quantum well field effect transistors with high-k gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications. Int Electron Dev Meeting (IEDM) Tech Dig 2010:126–9. [7] Terao R. InP/InGaAs composite metal-oxide-semiconductor field effect transistors with regrown source and Al2O3 gate dielectric exhibiting maximum drain current exceeding 1.3 mA/mm. Appl Phys Exp 2011;4:054201. [8] Egard M, Ohlsson L, Borg BM, Lenrick F, Wallenberg R, Wernersson L-E, et al. High Transconductance self-aligned gate-last surface channel In0.53Ga0.47As MOSFET. Int Electron Devices Meeting (IEDM) Tech Dig 2011:303–6. [9] Kim TW, Hill RJW, Young CD, Veksler D, Morassi L, Oktybrshky S et al. InAs Quantum-Well MOSFET (Lg = 100 nm) with record high gm, fT and fmax. In: Symposium on VLSI technology digest; 2012. p. 179–180. [10] Wu YQ, Wang WK, Koybasi O, Zakharov DN, Stach EA, Nakahara S, et al. 0.8-V supply voltage deep-submicrometer inversion-mode In0.75Ga0.25As MOSFET. IEEE Electron Dev Lett (EDL) 2009;30(7):700–2.

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