Characterization of impact of process options in Germanium-On-Insulator (GeOI) high-k & metal gate pMOSFETs by low-frequency noise

Solid-State Electronics 59 (2011) 34–38

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Characterization of impact of process options in Germanium-On-Insulator (GeOI) high-k & metal gate pMOSFETs by low-frequency noise M. Valenza a,⇑, J. Gyani a, F. Martinez a, S. Soliveres a, C. Le Royer b, E. Augendre b, L. Clavelier b a b

IES, Universite Montpellier II, UMR CNRS 5214, Place E. Bataillon, 34095 Montpellier Cedex 5, France CEA-LETI Minatec, 17 rue des Martyrs, 38054 Grenoble cedex 9, France

a r t i c l e

i n f o

Article history: Available online 4 March 2011 Keywords: PMOS GeOI 1/f noise

a b s t r a c t The impact of technological processes on Germanium-On-Insulator (GeOI) noise performance is studied. We present an experimental investigation of low-frequency noise (LFN) measurements carried out on (GeOI) PMOS transistors with different process splits. The front gate is composed of a SiO2/HfO2 stack with a TiN metal gate electrode. The result is an aggressively reduced equivalent oxide thickness (EOT) of 1.8 nm. The buried oxide is used as a back gate for experimental purposes. Front and back gate interfaces are characterized and the slow oxide trap densities are extracted. The obtained values are comprised between 5  1017 and 8  1018 cm3eV1. No correlation between front interface trap density and front interface mobility is observed. We underline a strong correlation between rear interface trap density and rear interface mobility degradation. The impact of Ge film thickness is equally studied. For thin films, the measured drain-current noise spectral density shows that LFN can be described by the carrier fluctuation model from weak to strong inversion. For thicker film devices, in weak inversion the LFN can be described by the mobility fluctuation model and in strong inversion the LFN is described by the carrier fluctuation model. The aH parameter for these devices is 1.2  103. These results are significant for the future development of GeOI technologies. Ó 2011 Published by Elsevier Ltd.

1. Introduction Novel materials and architectures have greatly contributed to the remarkable progress in MOSFET performance. Germanium (Ge) is a promising candidate to achieve sub-22 nm node high performance pMOSFETs thanks to its higher hole mobility compared to Silicon (Si). Furthermore, thin film fully depleted SOI MOSFET devices attract great interest as they present many advantages over bulk transistor technology such as high transconductance, improved sub-threshold slope and short channel effect (SCE) control, and suppression of the latch-up in CMOS technology [1]. Germanium-On-Insulator (GeOI) technology is therefore considered a serious contender to bulk silicon devices [2,3]. Nevertheless, parameters such as the threshold voltage, the mobility and the sub-threshold slope can be influenced by the back interface quality in ultra-thin film devices due the coupling between front and back depletion regions. It is therefore crucial to be able to determine the impact of GeOI fabrication processes on the quality of these two interfaces. Noise investigations are carried out for devices with different process options: three different As ion implantations and four ⇑ Corresponding author. Tel.: +33 04 67 14 32 27. E-mail address: [email protected] (M. Valenza). 0038-1101/$ - see front matter Ó 2011 Published by Elsevier Ltd. doi:10.1016/j.sse.2011.01.015

types of halo implantation. Halo implantations are formed with ions that are of opposite type to the source and drain doping, and are carried out with the aim of reducing short channel effects. We present results showing the influence of As ion implantation on the trap density at the Ge/buried oxide (BOx) interface in state of the art GeOI devices using low-frequency noise characterization. We also investigate the impact of halo implantations on the front and back gate trap density. Finally we show the impact of the Ge film thickness on noise characterization. 2. Theoretical considerations The 1/f noise is the result of fluctuations in the conductivity of metals and semiconductors. The 1/f noise can be modelled through two main physical phenomena: fluctuations in the number of carriers (DN) and the fluctuation of mobility (Dl). The DN model assumes that the fluctuation of the number of insulator charges induces fluctuations in the flat-band voltage. The relative drain-current noise power spectral density is expressed as [4]:

SID ðf Þ I2D

¼

 2 gm SVFB ðf Þ ID

ð1Þ

35

M. Valenza et al. / Solid-State Electronics 59 (2011) 34–38

The fluctuation of the oxide charge per unit area induces the fluctuation of the surface potential which is modelled by an equivalent flat-band voltage fluctuation. In the case where the slow oxide trap distribution is uniform in energy and in space we have a pure 1/f noise and the flat-band voltage fluctuation PSD is expressed as [4]:

SVFB ðf Þ ¼

q2 kTN t ðEF Þ

ð2Þ

cWLC 2ox f

where c is the tunnelling parameter and Nt(EF) is the slow oxide trap volume density. In order to extract trap densities at the front interface, it is necessary to take into account the specificities of the high-k front gate structure to obtain the tunnelling parameter c. According to McWorter’s model, low-frequency noise is generated by the trapping and de-trapping mechanism of charged carriers between traps in the oxide and the channel. The trapping mechanism can be modelled by calculating the probability of the transmission by quantum tunnelling of the carriers from the channel to the traps in the oxide. This calculation can be carried out using the Wentzel–Kramers–Brillouin approximation of Schrödinger’s equation. Using this approach, the wave function can be described using the following equations:

WðxÞ ¼ a cos for

Z

 dx h þ / with kðxÞ ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi k 2m ½e  VðxÞ

e > VðxÞ

ð3Þ

WðxÞ ¼ g exp

Z

  Z  dx dx þ d exp  with lðxÞ l l

 h ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi for 2m ½VðxÞ  e

e < VðxÞ

Time constant τ (s)

10

10

10

5

10

0

10

-5

SID ðf Þ ¼

aH fN

I2D

ð7Þ

where aH is the Hooge parameter used as a characteristic parameter for a given technology and N the total number of carriers under the gate. In weak inversion Rhayem et al. [7] have shown that Eq. (4) becomes:

2lkT aH qV ID tanhð 0 D Þ 2g kT L2 f

ð8Þ

g0 is the ideality factor related to drain biases.

ft ðEÞ

15

ð6Þ

The parameter c corresponds to the slope of the segment in Fig. 1 and is extracted from using Eq. (6). The extracted value for c is around 4.2  109 m1. This value varies with the applied gate voltage, but the variation is sufficiently small to be neglected. The Dl model is associated with mobility fluctuations and is described by the following empirical relation proposed by Hooge [6]:

ð4Þ

ð5Þ

rn f ðeÞNinv ðeÞTðe; xÞ

10

s ¼ s0 expðcxÞ

SID ðf Þ ¼ g0

where a, u, g, d are integration constants that insure the continuity of the wave functions between the different layers in the high-k gate stack. V(x) is the potential profile of the gate structure, and e is the incident electron energy. m is the effective mass in the HfO2 dielectric (=0.18 m0 for HfO2 [5]. The potential profile of the gate stack as a function of gate voltage, as well as the incident carrier energy are determined using a 1D Poisson–Schrodinger solver. The carrier transmission T(x) is then determined by multiplying the wave function with its conjugate and normalizing this term so that T(x) at the interface is unity. This value is then used to determine the trap time constant s using the following relationship:

s¼

Fig. 1 shows the calculated time constant s as a function of depth for SiO2 and SiO2/HfO2 gate stacks. The segment between 0 and 1 nm depth represents the SiO2 buffer layer, and the segment between 1 and 5 nm represents the HfO2 layer. LFN investigations are typically carried out between 1 Hz and 105 Hz. In this case, traps located in the first 1 nm are not probed. We may therefore ignore the SiO2 layer as the frequency of the trap activity at this depth correspond to a portion of the spectra that is difficult to exploit experimentally using usual low-frequency noise analysis methods. Therefore only the HfO2 segment needs to be modelled. This is done using the following relationship:

VG=0.5V

TiN

For low drain biases, Eq. (7) can be written as

SID ðf Þ ¼

ql a H ID V D L2 f

ð9Þ

According to Eqs. (7) and (8), the normalized drain-current noise PSD SID =I2D varies as I1 D in weak inversion. 3. Experimental details Low-frequency drain-current noise investigations are carried out on TiN/HfO2/SiO2 GeOI pMOSFETs with low equivalent oxide thickness (EOT) value. The studied devices are elaborated on 200 mm GeOI substrates with a 40–140 nm thick Ge active layer obtained using SmartCutTM technology. The devices were fabricated using GeOI transistor processes similar to those reported in [2,3], with thin Si capping passivation (1 nm) between the Ge and HfO2 layers. The Si capping layer growth is carried out at temperatures between 550 °C and 650 °C [8]. The front gate stack

SiO2 TiN

PolySi

HfO2

4nm HfO2 TiN 10nm

P+ P++

SiO2/Si

Ge ~80nm

P+ P++

Ge ~80nm

SiO2

10

BOx 200nm

-10

0

2

4

6

Depth x (nm) Fig. 1. Evolution of calculated time constant as a function of depth from Ge/SiO2 interface layer.

BOx 200nm Si Fig. 2. Schematics (left) and TEM image (right) of GeOI pMOSFETs [2].

M. Valenza et al. / Solid-State Electronics 59 (2011) 34–38

Halo implantation

A1 B1 C1 C2 C3 C4 C5 D1 D2 D3 D4

None None Doping1 Doping 1 Doping 2 Doping 2 Doping 2 Doping 1 None Doping 1 Doping 1

None None Halo2 None Halo1 Halo2 Halo3 None None None None

1e-4 1e-5

ΔN Model Experimental data

1e-6 1e-7 1e-8 1e-9 1e-10 1e-9

1e-8

4. Results and discussion 4.1. Front trap interface characterization Typical DC drain current evolutions versus front gate voltage VFG have shown a back conduction due to an apparent p type doping in the Ge film for devices that were fabricated without As ion implantation. For these devices, the back interface transistor is switched off by applying a back gate voltage of +60 V to the bottom of the wafer and the measured current is attributed solely to the front interface transistor.

1e-7

1e-6

1e-5

1e-4

ID (A) Fig. 3. Typical variation of the normalized front drain-current noise power spectral density at f = 1 Hz as a function of the drain current ID from weak to strong inversion, comparison with DN model, at VDS = 50 mV.

1e+19 No counter-doping Counter doping 1 Counter doping 2

C3

-3

exhibits an EOT of 1.8 nm. The SiO2 buried oxide layer (BOx) has a thickness varying between 200 nm and 300 nm, depending on the wafer (see Fig. 2). These devices show large ON state current densities with a perfect 1/LG behavior down to 120 nm, where LG is the gate length. These performances are due to large hole low field mobility, which has been shown to be constant with gate length scaling. The measured sub-threshold slope is between 100 and 140 mV/dec, which is larger than the kT/q limit = 60 mV/dec at room temperature. This is attributed to the interface state density (Dit) located at the interface between the Ge film substrate and the gate stack. In order to study the effects of doping, three different As ion implantations, each with different energy and dose conditions, were carried out on different devices (Doping1, Doping2 and No Doping). Furthermore, some devices also underwent halo implantation to control short channel effects. In order to study the effects of halo implantation, four types of halo implantation, each with different energy and dose conditions, were carried out on different devices (Halo1, Halo2, Halo3 and No Halo). These different splits are shown Table 1. It should be noted that the dopant implantation is carried out after the substrate elaboration but prior to gate stack deposition. Halo implantation is carried out after gate stack deposition. The studied devices have a width W = 1 lm and a length L between 0.12 and 5 lm. A complete current–voltage characterization using an Agilent 4156C semiconductor parameter analyzer was carried out prior to noise measurements. Low-frequency noise measurements were done using a HP89410A dynamic signal analyzer loaded by a high sensitivity current/voltage converter EG&G 5182. In order to measure the electrical characteristics at the Ge/ buried oxide (BOx) interface, the back of the substrate is polarised (VBG) in order to modulate back interface current. Furthermore, a voltage is applied to the front gate (VFG) to suppress the front interface channel conduction. Noise measurements were carried out at VDS = 50 mV, and from weak to strong inversion. The front and back interface mobilities were extracted using the Y function method [9].

D

Substrate doping

SI /ID2@1Hz (/Hz)

Device

The threshold voltage of the front interface transistor is between 0.2 V and 0.5 V and is a function of gate length. The extracted mobilities are reported in Fig 4. Values vary between 120 cm2/V s. and 360 cm2/V s. It can also be seen that devices having received halo implantation tend to have lower mobilities although sample C2 with no halo implantation also shows low mobility. Furthermore, it can be seen that devices without substrate doping exhibit the highest mobility values. Noise measurements for front interface characterization were carried out on thin Ge film devices (>80 nm) with VFG varying between 0.5 V and 1.2 V, with VDS = 50 mV and VBG at +60 V for non doped devices and 0 V for doped devices. The measured spectra show that 1/f noise is predominant. Fig. 3 shows typical normalized drain-current noise power spectral density SID =I2D at f = 1 Hz as a function of the drain current ID from weak to strong inversion. The observed behavior indicates that the noise fluctuations follow the DN carrier number fluctuation model. Using Eqs. (1) and (2), the slow oxide trap density NT(EF) of the front oxide can be extracted. The obtained values are comprised between 7  1017 cm3eV1.and 2  1018 cm3eV1. Fig. 4 shows the trap density at the Ge/front oxide interface as a function of carrier mobility for the different studied devices. It can be seen that there is no correlation between the trap density and the mobility; the trap density values in the devices studied show little dispersion.

-1

Table 1 Technological characteristics of studied devices.

Trap Density (cm eV )

36

C2 C5

B1

1e+18

A1

D3

C1 D4

D2

D1

1e+17 100

150

200

250

300

350

400

Mobility (cm2 V -1s-1) Fig. 4. Evolution of extracted front interface trap densities as a function of carrier mobility.

37

M. Valenza et al. / Solid-State Electronics 59 (2011) 34–38

4.2. Back trap interface characterization

1e+19 D1

5e-6

1e-7

4e-6

8e-8

3e-6

6e-8

2e-6

4e-8

1e-6

2e-8

0

0

40

20

0

-20

-40

-60

-80

-2e-8 -100

Back channel transconductance gm (S)

Back channel current ID (A)

Back gate voltage VBG (V)

-1 -3

D3

1e+17 50

10-11 10-9

10-8

10-7

10-5

10-4

ID (A) Fig. 6. Typical variation of the normalized back drain-current noise power spectral density at f = 1 Hz as a function of the drain current ID from weak to strong inversion, comparison with DN model at VDS = 50 mV.

200

250

300

350

-1 -1

Fig. 7. Evolution of extracted back interface trap densities as a function of carrier mobility.

more, the impact of substrate dopant implantation is clearly shown; devices with substrate doping show a threefold reduction in rear channel mobility and up to a ten-fold increase rear interface trap density. By comparing the trap densities as a function of mobility for front and back interfaces of the different devices, it can be seen that substrate doping ion implantation affects trap density at the rear interface only, suggesting that the actual ion implantation process creates defects at the rear interface through direct collision. 4.3. Effect of Ge film thickness In order to study the impact of film thickness, devices with various Ge film thicknesses between 40 nm and 140 nm were measured. Front drain-current noise measurements have been carried out from weak to strong inversion and were carried out as a function of the Ge film thickness. Fig. 8 shows typical normalized drain-current noise power spectral density SID =I2D at f = 1 Hz as a function of the drain current ID from weak to strong inversion. We observe two different behaviors in weak inversion, whereas in strong inversion the same behavior is observed. For thin films, the measured drain-current noise PSD shows that LFN can be described by the carrier fluctuation model from weak to strong inversion. For thicker film devices, in weak inversion the LFN can be described by the mobility fluctu-

D

10-6

150

2

(-1) slope

10-6 10-7 10-8 10-9

10-10

100

Mobility (cm V s )

SI /ID2@1Hz (/Hz)

D

Experimental data ΔΝ Model

D2 A1

10-5

10-9

C3

B1

10-6

10-8

No counter-doping Counter doping 1 Counter doping 2

C4

1e+18

10-4

10-7

C2 C1

10-5

-1

SI /ID²@1 Hz (Hz )

Fig. 5. Typical variation of the back gate ID/VBG characteristics and gm/VBG, VDS = 50 mV, W = 1 lm.

C5

D4

Trap Density (cm eV )

The front interface transistor is switched off at VFG = 0.5 V and the measured current is solely attributed to the back interface transistor. VDS = 50 mV. The back interface drain current and conductance (gm) evolutions versus back gate voltage VBG for a given front gate voltage VFG show normal transistor operation. (see Fig. 5). Back gate threshold voltage and carrier mobilities are extracted. For devices without substrate doping the threshold voltages are about 10 V, whereas for devices with substrate doping the threshold voltage are between 20 V and 30 V. The extracted mobilities are between 80 and 300 cm2/V s. (see Fig 7). Noise measurements for back interface characterization were carried out under the same polarisation conditions than for the static measurements. Typical normalized drain current spectral density carried out at 1 Hz is reported as a function of drain current in Fig. 6. The 1/f noise power spectral density (PSD) measured at the back interface follows McWorter’s number fluctuation (DN) model described by Eqs. (1) and (2), and is therefore attributed to charge trapping by slow oxide traps in the BOx. Following this model, the slow oxide trap density NT(EF) of the BOx can be extracted. The obtained values are comprised between 5  1017 and 8  1018 cm3eV1. Fig. 7 shows the variation of the trap density at the Ge/buried oxide (BOx) interface as a function of the carrier mobility for the different studied devices. It can be seen that there is a correlation between the trap density and the mobility. Further-

10-10 10-9

Thick film experimental data Thin film ΔN model Thin film experimental data

10-8

10-7

10-6

10-5

10-4

ID (A) Fig. 8. Typical variation of the normalized drain current at f = 1 Hz as a function of the drain current ID from weak to strong inversion for thick and fin Ge film, comparison with DN model data.

38

M. Valenza et al. / Solid-State Electronics 59 (2011) 34–38

ation model and in strong inversion the LFN is described by carrier fluctuation model. This behavior can be explained by the fact that for thicker devices the noise attributed to volume conduction is predominant compared to noise attributed to surface conduction. Eq. (7) is used to extract the value of Hooge’s parameter, which is found to be aH = 1.2  103. This value is slightly above the range reported for conventional bulk CMOS devices (SiO2/poly-Si gate stack) [10], but is of the same order as that originally found by Hooge in germanium bars [11]. To the author’s knowledge, there are no published values of aH for advanced Ge/high-k devices.

having not received implantation. The study also suggests substrate doping by ion implantation creates defects at the rear interface. The effect of halo implantation is shown to be negligible in comparison to the effects of substrate doping. For thick Ge film devices, front interface noise behavior in weak inversion can be described by the mobility fluctuation model, and by carriers number fluctuations model in strong inversion. Hooge’s parameter, is found to be aH = 1.2  103. This value is slightly above the range reported for conventional bulk CMOS devices (SiO2/poly-Si gate stack) [8], but is of the same order as that originally found by Hooge in germanium bars [9].

5. Conclusion Acknowledgements We have investigated front and rear interface 1/f noise in Ge pMOSFETs from weak to strong inversion for several devices with various Ge film thicknesses between 40 nm and 140 nm and with various technological processes, including substrate doping and Halo implantations. For thin Ge film devices, from weak to strong inversion, we have found that noise originates in the fluctuation of the number of carriers (DN model) caused by trapping and de-trapping via defects in the dielectric oxides. Front and rear trap densities were extracted for all devices and correlated to the extracted low-field carrier mobilities. For the front interface, no correlation is observed between trap densities and carrier mobilities. For the rear interface, we have shown the impact of ion implantation doping of the substrate film on the trap density. Trap densities are 10 times higher in samples having undergone ion implantation compared to those

The authors thank French OSEO organisation for financial support. References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]

Skotnicki T. Microelectron Eng 2007;84:1845–52. Le Royer C et al. Solid-State Electron 2008;52:285–1290. Romanjek K et al. SOI conf 2008:147–8. Ghibaudo G. Solid-State Electron 1987;30:1037. Srinivasan P et al. Mater Sci Semicond Process 2006;9:721–6. Hooge FN. Phys Lett A 1969;29:139. Rhayem J et al. J Appl Phys 2001;89(7):4192–4. Hartmann JM et al. Semicond. Sci. Technol 2009;24:055002. Ghibaudo H. Haddara editors. Kluwer Academic Publishers; 1995 [chapter 1]. Haartman MV, Hostling M. Dordrecht. Netherlands: Springer; 2007. Hooge FN et al. Rep Prog Phys 1981;44(5):497–532.