- Email: [email protected]
metal gate pMOSFETs
Microelectronics Reliability 53 (2013) 1351–1354
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Effect of negative bias temperature instability induced by a low stress voltage on nanoscale high-k/metal gate pMOSFETs Seonhaeng Lee ⇑, Cheolgyu Kim, Hyeokjin Kim, Gang-Jun Kim, Ji-Hoon Seo, Donghee Son, Bongkoo Kang Department of Electrical Engineering, Pohang University of Science and Technology, Pohang, Gyeongbuk 790-784, Republic of Korea
a r t i c l e
i n f o
Article history: Received 23 May 2013 Received in revised form 20 June 2013 Accepted 6 July 2013
a b s t r a c t The effect of a low stress voltage on the negative bias temperature instability degradation in a nanoscale p-channel metal–oxide–semiconductor field-effect transistor using high-k/metal gate stacks is investigated. The direct current–current voltage and carrier separation methods are used to separate the effects of electrons and holes. The results indicate that a high stress voltage generates positive oxide charges that degrade the device, but a low stress voltage generates negative oxide charges that induce the turn-around effect of the threshold voltage. Ó 2013 Elsevier Ltd. All rights reserved.
1. Introduction The physical thickness of gate oxides in semiconductor transistors has continued to scale down along with the overall device dimensions, owing to the desire for more compact devices. As the device scales down, the gate tunnelling increases and negatively affects the performance of the devices. Thus, thick high-k metal gate stacks, which have the same equivalent oxide thickness as SiO2, have been used to block the direct tunneling of carriers through the gate oxide. Hf-based oxides such as HfO2 and HfSiOxNy are the most promising materials that have been proposed to date [1,2]. Although the high-k/metal gate stacks prevent the gate tunneling leakage current, pre-existing defects cause many reliability problems such as a mobility degradation, shift in threshold voltage Vth, and bias temperature instability (BTI) [3–5]. Pre-existing defects can cause remote coulomb scattering and remote phonon scattering, which degrade carrier mobility [3]. Because of the presence of pre-existing trap defects, the trapping and de-trapping of electrons and holes induce serious BTI problems. Jung et al. reported that threshold voltage shift DVth in an n-channel metal–oxide–semiconductor field-effect transistor (nMOSFET) experienced positive bias temperature instability (PBTI), which was caused by electrontrapped charges [5]. They also reported that DVth in a pMOSFET experienced negative bias temperature instability (NBTI), which was caused by hole-trapped charges and interface trap charges [5]. Many researchers have reported on the turn-around effect of Vth in high-k/metal gate nMOSFETs under PBTI stress [5,6]. The turnaround effect occurred when the stress voltage was high and was attributed to hole trapping [6]. Therefore, the turn-around effect should be considered when predicting the device lifetime. For the high-k/metal gate pMOSFETs, the degradation mechanism of the ⇑ Corresponding author. Tel.: +82 (54) 279 5939; fax: +82 (54) 279 2903. E-mail address: [email protected] (S. Lee). 0026-2714/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2013.07.026
NBTI caused by oxide charges and interface trap charges has been investigated in detail, but the cause of the turn-around effect of Vth has not. Thus, the turn-around effect caused by the NBTI stress should be investigated to gain deeper insight into the Vth behavior. This paper investigates the effect of a low stress voltage on NBTI degradation in a nanoscale high-k/metal gate pMOSFET. The experimental setup is detailed in Section 2. Changes in DVth due to the NBTI stress are described in Section 3, and the cause of the device degradation is discussed. Finally, the conclusion is presented in Section 4. 2. Experimental setup The high-k/metal gate pMOSFETs for the experiments were fabricated by using the sub-100 nm CMOS technology. The devices were n+ poly-Si gate pMOSFETs with a gate length and width of 70 nm and 10 lm, respectively. A gate-first process was employed with a TiN/HfSiON gate stack. The thickness of the HfSiON layer was 5 nm, and the thickness of the SiON interfacial layer was 1 nm. SiGe was used for the channel layer. NBTI stress voltages of 1.9 and 2.5 V were applied to the gate voltage Vg at a temperature T = 125 °C, whereas the drain Vd, source Vs, and substrate Vb voltages were grounded. The stress voltage was periodically interrupted to measure Vth, the gate induced drain leakage current (IGIDL), the drain current (Id), the off leakage current (Ioff), and the pn junction leakage current density (JPN) with a HP4156A semiconductor parameter analyzer. DVth was defined as the Vg resulting in an Id = 2 lA/lm, and for all measurements, T was 125 °C. 3. Results and discussion While applying the gate stress voltage Vg,str = 2.5 V, DVth was measured as a function of the NBTI stress time (see Fig. 1). The
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S. Lee et al. / Microelectronics Reliability 53 (2013) 1351–1354
Fig. 1. DVth versus NBTI stress time for T = 125 °C. (Inset)|Id|–Vg curves measured for Vd = 50 mV during the NBTI stress (Vg,str = 2.5 V) period.
NBTI stress increased D|Vth| by 240 mV for a stress time of 2000 s. Typically, the NBTI stress generates a positive oxide charge Qox and positively charged donor-like interface state Nit [4,5]. To determine the generation of Qox and Nit, Id and subthreshold slope SS were measured. The shifting of the Id curve reflects the creation of Qox. Changes in Nit were determined by measuring the SS oVg/o (logId) because SS reflects the effects of Nit [7] (see Fig. 1, inset). A small amount of SS changed under the NBTI stress, which indicates changes in Nit. In addition, IGIDL and Ioff were measured (see Fig. 2). IGIDL increased by 57.6% for a stress time of 2000 s. Ioff decreased by 98.8% for a stress time of 2000 s. Shifts of both IGIDL and Ioff confirm that Qox is generated; Qox at the drain extension increases the surface potential but decreases the oxide field. These results indicate that the NBTI stress generates Qox and Nit. To further understand the effects of the NBTI stress, JPN was measured using the direct current–current voltage (DCIV) method (see Fig. 3). The increase in the peak value of JPN reflects the generation of Nit, and the shift in Vg,peak (DVg,peak), reflects the generation of Qox (see Fig. 3) [8]. (Vg,peak is defined as the Vg resulting in the peak value of JPN). The measurement results show that the NBTI stress generates Qox and Nit. Moreover, the values of the time exponent (n) of DVth, DJPN, and DVg,peak were measured to determine the cause of the NBTI degradation. The extracted n values were n = 0.08, 0.41, 0.08 for D|Vth|, D|JPN|, and |DVg,peak|, respectively (see Fig. 4). It is clear that n for D|Vth| and n for |DVg,peak| are the same. Consequently, the NBTI stress under Vg,str = 2.5 V creates Qox and Nit, and the dominant cause of the NBTI degradation is the generation of Qox. Next, the effect of the low stress voltage Vg,str = 1.9 V on the experimental device was investigated. DVth was measured as a
Fig. 2. |Id|–Vg curves measured at Vd =
1.5 V during the NBTI stress period.
Fig. 3. |JPN| versus Vg measured at Vd = 0.1 V during the NBTI stress (Vg,str = period.
2.5 V)
Fig. 4. D|Vth| and D|Vg,peak| versus NBTI stress time measured at 125 °C. (a) Time exponent n of D|Vth| was extracted. (b) Time exponent n of |DVg,peak| was extracted. Inset: Time exponent n of D|JPN| was extracted.
Fig. 5. D|Vth| versus NBTI stress time for T = 125 °C (Vg,str =
1.9 V).
S. Lee et al. / Microelectronics Reliability 53 (2013) 1351–1354
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Fig. 6. Percentile changes in the electron and hole currents versus NBTI stress time at 125 °C. (a) NBTI stress of Vg,str = 2.5 V was applied, and shifts of electron and hole current were measured when Vg = 2 V. (b) NBTI stress ofVg,str = 1.9 V was applied, and shifts of electron and hole current were measured when Vg = 2 V.
Fig. 7. Energy band diagram when Vg = Vg,str = 1.9 V.
1.9 V after NBTI stressed with
in Ihole was caused by the high electric field and the increase of trap-assisted tunneling currents (see Fig. 6a). However, Ielec under Vg,str = 1.9 V decreased (see Fig. 6b). Ihole under Vg,str = 1.9 V also decreased, but it slowly increased after 100 s. This results indicate the generation of Q ox ; Q ox reduces the internal electric field and results in a decrease in Ielec. During the same time, Qox is created by hole trapping, so Ihole increases slowly. Furthermore, the barrier height for the electron tunneling is lower than the barrier height for the hole tunneling, so the electron tunneling current can generate more traps than does the hole tunneling current (see Fig. 7). Consequently, the NBTI stress while applying low Vg,str generates Q ox created by the electron trapping such that the turn-around effect occurs. In addition, JPN using the DCIV method was measured (see Fig. 8). D|JPN| did not change, but |DVg,peak| increased by 5% for a stress time of 100 s. This result confirms that Qox is generated until 100 s has passed. After 100 s, |DVg,peak| decreased, and D|JPN| increased. This result confirms that both Q ox and Nit are created after 100 s. These observations and the observed turn-around effect of D|Vth| show the same behavior. Thus, the turn-around effect of D|Vth| is caused by Q ox . Our results of D|Vth|, |DVg,peak|, D|JPN| indicate that defects induced by electrons and holes should be taken seriously when evaluating the device reliability because differences in stress voltage can change the degradation mechanism of the NBTI. 4. Conclusion
Fig. 8. |JPN| versus Vg measured at Vd = 0.1 V during the NBTI stress (Vg,str = period.
1.9 V)
function of the NBTI stress time (see Fig. 5). Vth increased until 30 s, but it decreased continuously after that period. This is called the turn-around effect [6]. Although the turn-around effect typically occurs in high-k/metal gate nMOSFETs because of hole trapping, in case of the experimental high-k/metal gate pMOSFET, a decrease in DVth indicates the generation of the negative oxide charge Q ox . Thus, the carrier separation method [9], which can separate electron and hole currents, was used to investigate the turn-around effect. The shifts of the electron current Ielec and the hole current Ihole were measured (see Fig. 6). Ielec and Ihole increased when Vg,str = 2.5 V. Qox generated by hole trapping enhances the internal electric field, and causes an increase in Ielec. In the case of Ihole, the current decreased after 1 s, but then immediately started to increase. The decrease in Ihole was caused by the enhanced barrier height of the valence band of the dielectric layer, and the increase
The effect of the NBTI stress with the low stress voltage on a high-k/metal gate pMOSFET was investigated. A high and low NBTI stress voltage was applied, and the DCIV and carrier separation methods were used to investigate the effect of electrons and holes separately. Experimental data indicate that positively charged donor-like interface states and positive oxide charges Qox were created by a high NBTI stress voltage (Vg,str = 2.5 V), whereas negative oxide charges Q ox were created by a low NBTI stress voltage (Vg,str = 1.9 V). Qox was the cause of the NBTI degradation while applying Vg,str = 2.5 V. The turn-around effect of DVth occurred while applying Vg,str = 1.9 V and was observed to be caused by Q ox . These experimental observations suggest that the turn-around effect should be considered when evaluating device reliability Acknowledgements This work was supported by the BK21 Program, IT Consilience Creative Program of MKE and NIPA (C1515-1121-0003), and SK hynix Inc., Korea. References [1] Gutowski M, Jaffe JE, Liu CL, Stoker M, Hegde RI, Rai RS, et al. Appl Phys Lett 2002;80(11):1897–9.
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S. Lee et al. / Microelectronics Reliability 53 (2013) 1351–1354
[2] Visokay MR, Chambers JJ, Rotondaro ALP, Shanware A, Colombo L. Appl Phys Lett 2002;80(17):3183–5. [3] Robertson J. Rep Progr Phys 2006;69(2):327–96. [4] Zafar S, Kumar A, Gusev E, Cartier E. IEEE Trans Dev Mater Reliab 2005;5(1):45–63. [5] Jung H-S, Kim JH, Lee J, Lee SY, Kim UK, Hwang CS, et al. J Electrochem Soc 2010;157(3):H334–60.
[6] Rhee SJ, Lee JC. Microelectron Reliab 2005;45:1051–60. [7] Hu C, Tam SC, Hsu F-C, Ko P-K, Chan T-Y, Terrill KW. IEEE J Solid-State Circ 1985;SSC-20(1):295–305. [8] Zhu S, Nakajima A, Ohashi T, Miyake H. J Appl Phys 2005;98:114504. [9] Mizubayashi W, Yasuda N, Okada K, Ota H, Hisamatsu H, Iwamoto K, et al. Microelectron Reliab 2005;45:1041–50.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
Effect of negative bias temperature instability induced by a low stress voltage on nanoscale high-k/metal gate pMOSFETs Seonhaeng Lee ⇑, Cheolgyu Kim, Hyeokjin Kim, Gang-Jun Kim, Ji-Hoon Seo, Donghee Son, Bongkoo Kang Department of Electrical Engineering, Pohang University of Science and Technology, Pohang, Gyeongbuk 790-784, Republic of Korea
a r t i c l e
i n f o
Article history: Received 23 May 2013 Received in revised form 20 June 2013 Accepted 6 July 2013
a b s t r a c t The effect of a low stress voltage on the negative bias temperature instability degradation in a nanoscale p-channel metal–oxide–semiconductor field-effect transistor using high-k/metal gate stacks is investigated. The direct current–current voltage and carrier separation methods are used to separate the effects of electrons and holes. The results indicate that a high stress voltage generates positive oxide charges that degrade the device, but a low stress voltage generates negative oxide charges that induce the turn-around effect of the threshold voltage. Ó 2013 Elsevier Ltd. All rights reserved.
1. Introduction The physical thickness of gate oxides in semiconductor transistors has continued to scale down along with the overall device dimensions, owing to the desire for more compact devices. As the device scales down, the gate tunnelling increases and negatively affects the performance of the devices. Thus, thick high-k metal gate stacks, which have the same equivalent oxide thickness as SiO2, have been used to block the direct tunneling of carriers through the gate oxide. Hf-based oxides such as HfO2 and HfSiOxNy are the most promising materials that have been proposed to date [1,2]. Although the high-k/metal gate stacks prevent the gate tunneling leakage current, pre-existing defects cause many reliability problems such as a mobility degradation, shift in threshold voltage Vth, and bias temperature instability (BTI) [3–5]. Pre-existing defects can cause remote coulomb scattering and remote phonon scattering, which degrade carrier mobility [3]. Because of the presence of pre-existing trap defects, the trapping and de-trapping of electrons and holes induce serious BTI problems. Jung et al. reported that threshold voltage shift DVth in an n-channel metal–oxide–semiconductor field-effect transistor (nMOSFET) experienced positive bias temperature instability (PBTI), which was caused by electrontrapped charges [5]. They also reported that DVth in a pMOSFET experienced negative bias temperature instability (NBTI), which was caused by hole-trapped charges and interface trap charges [5]. Many researchers have reported on the turn-around effect of Vth in high-k/metal gate nMOSFETs under PBTI stress [5,6]. The turnaround effect occurred when the stress voltage was high and was attributed to hole trapping [6]. Therefore, the turn-around effect should be considered when predicting the device lifetime. For the high-k/metal gate pMOSFETs, the degradation mechanism of the ⇑ Corresponding author. Tel.: +82 (54) 279 5939; fax: +82 (54) 279 2903. E-mail address: [email protected] (S. Lee). 0026-2714/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2013.07.026
NBTI caused by oxide charges and interface trap charges has been investigated in detail, but the cause of the turn-around effect of Vth has not. Thus, the turn-around effect caused by the NBTI stress should be investigated to gain deeper insight into the Vth behavior. This paper investigates the effect of a low stress voltage on NBTI degradation in a nanoscale high-k/metal gate pMOSFET. The experimental setup is detailed in Section 2. Changes in DVth due to the NBTI stress are described in Section 3, and the cause of the device degradation is discussed. Finally, the conclusion is presented in Section 4. 2. Experimental setup The high-k/metal gate pMOSFETs for the experiments were fabricated by using the sub-100 nm CMOS technology. The devices were n+ poly-Si gate pMOSFETs with a gate length and width of 70 nm and 10 lm, respectively. A gate-first process was employed with a TiN/HfSiON gate stack. The thickness of the HfSiON layer was 5 nm, and the thickness of the SiON interfacial layer was 1 nm. SiGe was used for the channel layer. NBTI stress voltages of 1.9 and 2.5 V were applied to the gate voltage Vg at a temperature T = 125 °C, whereas the drain Vd, source Vs, and substrate Vb voltages were grounded. The stress voltage was periodically interrupted to measure Vth, the gate induced drain leakage current (IGIDL), the drain current (Id), the off leakage current (Ioff), and the pn junction leakage current density (JPN) with a HP4156A semiconductor parameter analyzer. DVth was defined as the Vg resulting in an Id = 2 lA/lm, and for all measurements, T was 125 °C. 3. Results and discussion While applying the gate stress voltage Vg,str = 2.5 V, DVth was measured as a function of the NBTI stress time (see Fig. 1). The
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S. Lee et al. / Microelectronics Reliability 53 (2013) 1351–1354
Fig. 1. DVth versus NBTI stress time for T = 125 °C. (Inset)|Id|–Vg curves measured for Vd = 50 mV during the NBTI stress (Vg,str = 2.5 V) period.
NBTI stress increased D|Vth| by 240 mV for a stress time of 2000 s. Typically, the NBTI stress generates a positive oxide charge Qox and positively charged donor-like interface state Nit [4,5]. To determine the generation of Qox and Nit, Id and subthreshold slope SS were measured. The shifting of the Id curve reflects the creation of Qox. Changes in Nit were determined by measuring the SS oVg/o (logId) because SS reflects the effects of Nit [7] (see Fig. 1, inset). A small amount of SS changed under the NBTI stress, which indicates changes in Nit. In addition, IGIDL and Ioff were measured (see Fig. 2). IGIDL increased by 57.6% for a stress time of 2000 s. Ioff decreased by 98.8% for a stress time of 2000 s. Shifts of both IGIDL and Ioff confirm that Qox is generated; Qox at the drain extension increases the surface potential but decreases the oxide field. These results indicate that the NBTI stress generates Qox and Nit. To further understand the effects of the NBTI stress, JPN was measured using the direct current–current voltage (DCIV) method (see Fig. 3). The increase in the peak value of JPN reflects the generation of Nit, and the shift in Vg,peak (DVg,peak), reflects the generation of Qox (see Fig. 3) [8]. (Vg,peak is defined as the Vg resulting in the peak value of JPN). The measurement results show that the NBTI stress generates Qox and Nit. Moreover, the values of the time exponent (n) of DVth, DJPN, and DVg,peak were measured to determine the cause of the NBTI degradation. The extracted n values were n = 0.08, 0.41, 0.08 for D|Vth|, D|JPN|, and |DVg,peak|, respectively (see Fig. 4). It is clear that n for D|Vth| and n for |DVg,peak| are the same. Consequently, the NBTI stress under Vg,str = 2.5 V creates Qox and Nit, and the dominant cause of the NBTI degradation is the generation of Qox. Next, the effect of the low stress voltage Vg,str = 1.9 V on the experimental device was investigated. DVth was measured as a
Fig. 2. |Id|–Vg curves measured at Vd =
1.5 V during the NBTI stress period.
Fig. 3. |JPN| versus Vg measured at Vd = 0.1 V during the NBTI stress (Vg,str = period.
2.5 V)
Fig. 4. D|Vth| and D|Vg,peak| versus NBTI stress time measured at 125 °C. (a) Time exponent n of D|Vth| was extracted. (b) Time exponent n of |DVg,peak| was extracted. Inset: Time exponent n of D|JPN| was extracted.
Fig. 5. D|Vth| versus NBTI stress time for T = 125 °C (Vg,str =
1.9 V).
S. Lee et al. / Microelectronics Reliability 53 (2013) 1351–1354
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Fig. 6. Percentile changes in the electron and hole currents versus NBTI stress time at 125 °C. (a) NBTI stress of Vg,str = 2.5 V was applied, and shifts of electron and hole current were measured when Vg = 2 V. (b) NBTI stress ofVg,str = 1.9 V was applied, and shifts of electron and hole current were measured when Vg = 2 V.
Fig. 7. Energy band diagram when Vg = Vg,str = 1.9 V.
1.9 V after NBTI stressed with
in Ihole was caused by the high electric field and the increase of trap-assisted tunneling currents (see Fig. 6a). However, Ielec under Vg,str = 1.9 V decreased (see Fig. 6b). Ihole under Vg,str = 1.9 V also decreased, but it slowly increased after 100 s. This results indicate the generation of Q ox ; Q ox reduces the internal electric field and results in a decrease in Ielec. During the same time, Qox is created by hole trapping, so Ihole increases slowly. Furthermore, the barrier height for the electron tunneling is lower than the barrier height for the hole tunneling, so the electron tunneling current can generate more traps than does the hole tunneling current (see Fig. 7). Consequently, the NBTI stress while applying low Vg,str generates Q ox created by the electron trapping such that the turn-around effect occurs. In addition, JPN using the DCIV method was measured (see Fig. 8). D|JPN| did not change, but |DVg,peak| increased by 5% for a stress time of 100 s. This result confirms that Qox is generated until 100 s has passed. After 100 s, |DVg,peak| decreased, and D|JPN| increased. This result confirms that both Q ox and Nit are created after 100 s. These observations and the observed turn-around effect of D|Vth| show the same behavior. Thus, the turn-around effect of D|Vth| is caused by Q ox . Our results of D|Vth|, |DVg,peak|, D|JPN| indicate that defects induced by electrons and holes should be taken seriously when evaluating the device reliability because differences in stress voltage can change the degradation mechanism of the NBTI. 4. Conclusion
Fig. 8. |JPN| versus Vg measured at Vd = 0.1 V during the NBTI stress (Vg,str = period.
1.9 V)
function of the NBTI stress time (see Fig. 5). Vth increased until 30 s, but it decreased continuously after that period. This is called the turn-around effect [6]. Although the turn-around effect typically occurs in high-k/metal gate nMOSFETs because of hole trapping, in case of the experimental high-k/metal gate pMOSFET, a decrease in DVth indicates the generation of the negative oxide charge Q ox . Thus, the carrier separation method [9], which can separate electron and hole currents, was used to investigate the turn-around effect. The shifts of the electron current Ielec and the hole current Ihole were measured (see Fig. 6). Ielec and Ihole increased when Vg,str = 2.5 V. Qox generated by hole trapping enhances the internal electric field, and causes an increase in Ielec. In the case of Ihole, the current decreased after 1 s, but then immediately started to increase. The decrease in Ihole was caused by the enhanced barrier height of the valence band of the dielectric layer, and the increase
The effect of the NBTI stress with the low stress voltage on a high-k/metal gate pMOSFET was investigated. A high and low NBTI stress voltage was applied, and the DCIV and carrier separation methods were used to investigate the effect of electrons and holes separately. Experimental data indicate that positively charged donor-like interface states and positive oxide charges Qox were created by a high NBTI stress voltage (Vg,str = 2.5 V), whereas negative oxide charges Q ox were created by a low NBTI stress voltage (Vg,str = 1.9 V). Qox was the cause of the NBTI degradation while applying Vg,str = 2.5 V. The turn-around effect of DVth occurred while applying Vg,str = 1.9 V and was observed to be caused by Q ox . These experimental observations suggest that the turn-around effect should be considered when evaluating device reliability Acknowledgements This work was supported by the BK21 Program, IT Consilience Creative Program of MKE and NIPA (C1515-1121-0003), and SK hynix Inc., Korea. References [1] Gutowski M, Jaffe JE, Liu CL, Stoker M, Hegde RI, Rai RS, et al. Appl Phys Lett 2002;80(11):1897–9.
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S. Lee et al. / Microelectronics Reliability 53 (2013) 1351–1354
[2] Visokay MR, Chambers JJ, Rotondaro ALP, Shanware A, Colombo L. Appl Phys Lett 2002;80(17):3183–5. [3] Robertson J. Rep Progr Phys 2006;69(2):327–96. [4] Zafar S, Kumar A, Gusev E, Cartier E. IEEE Trans Dev Mater Reliab 2005;5(1):45–63. [5] Jung H-S, Kim JH, Lee J, Lee SY, Kim UK, Hwang CS, et al. J Electrochem Soc 2010;157(3):H334–60.
[6] Rhee SJ, Lee JC. Microelectron Reliab 2005;45:1051–60. [7] Hu C, Tam SC, Hsu F-C, Ko P-K, Chan T-Y, Terrill KW. IEEE J Solid-State Circ 1985;SSC-20(1):295–305. [8] Zhu S, Nakajima A, Ohashi T, Miyake H. J Appl Phys 2005;98:114504. [9] Mizubayashi W, Yasuda N, Okada K, Ota H, Hisamatsu H, Iwamoto K, et al. Microelectron Reliab 2005;45:1041–50.