Enhanced ESD properties of GaN-based light-emitting diodes with various MOS capacitor designs

Superlattices and Microstructures 48 (2010) 23–30

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Enhanced ESD properties of GaN-based light-emitting diodes with various MOS capacitor designs P.C. Tsai a,b , W.R. Chen c , Y.K. Su a,b,d,∗ a

Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 70101, Taiwan, ROC

b

Advanced Optoelectronic Technology Center, National Cheng Kung University, Tainan 70101, Taiwan, ROC

c

Department of Electronic Engineering, National Formosa University, Yunlin 632, Taiwan, ROC

d

Department of Electrical Engineering, Kun Shan University, Tainan 710, Taiwan, ROC

article

info

Article history: Received 6 January 2010 Received in revised form 17 March 2010 Accepted 15 April 2010 Available online 20 May 2010 Keywords: GaN LED MOS Electrostatic discharge (ESD) Human body model (HBM)

abstract High electrostatic discharge (ESD) protection of GaN-based lightemitting diodes (LEDs) has been developed using a metal–oxide semiconductor (MOS) capacitor. This structure is realized by adopting various metal electrode patterns. The MOS capacitor can be implemented by extending the metal line directly from the ptype electrode to the top surface of an SiO2 -capped n-GaN layer near the vicinity of the n-type electrode. By connecting a MOS capacitor in parallel with the GaN-based LED, the negative ESD strike could be significantly increased from 385 to 1075 V of human body mode (HBM). © 2010 Elsevier Ltd. All rights reserved.

1. Introduction Nowadays, III-nitride semiconductor technology has reached a very mature stage, prompting a successful commercialization of numerous GaN-based devices operating in green, blue and ultraviolet spectral regimes [1,2]. These nitride-based materials possess excellent physical and chemical characteristics, such as wide direct band gap, high breakdown field, high thermal conductivity, high operating temperature, and stable chemistry, making them widely applicable in the areas of optoelectronic and electronic devices. In particular, the optoelectronic devices thus fabricated have been proven quite valuable in applications involving indication and illumination, including LEDs, laser

∗ Corresponding author at: Institute of Microelectronics, Department of Electrical Engineering, National Cheng Kung University, Tainan 70101, Taiwan, ROC. Tel.: +886 6 2351864; fax: +886 6 2356226. E-mail address: [email protected] (Y.K. Su). 0749-6036/$ – see front matter © 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.spmi.2010.04.006

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diodes (LDs), automobile lights, and full-color display backlight systems. As regards illumination, the white LED appears to be a promising candidate for replacing the conventional incandescent bulb and fluorescent lamp. Although GaN-based LEDs potentially have a wide variety of applications, some of the well-known issues limiting the device performances still require ingenious solutions: for instance, the ESD induced as result of growing GaN-based LEDs on insulating sapphire substrates. In general, GaN epilayers are usually grown on a sapphire substrate since no suitable substrates could be utilized for GaN-based LEDs or LDs. An LED exposed to an ESD event not only exhibits device degradation, but the very event may also result in personal hazard if the device is operated in a flammable environment. In recent years, several research groups have investigated ways to overcome the ESD-induced damage, such as combining a GaN-based LED with a Si-based Zener diode via the flip-chip process [3], building an internal GaN Schottky diode inside the LED chip using etching and redeposition techniques [4], inserting a high-temperature grown p-type cap layer into an epitaxial device structure [5,6], and building a shunt GaN p–n junction diode connected in an orientation inversely parallel to the GaN LED [7]. However, attaching a Si submount with Zener diode to a GaN-based LED requires a precise alignment if a flip-chip process is to be adopted, which potentially may lower the production yield. Furthermore, incorporating an internal GaN Schottky diode or a shunt GaN p–n junction diode with the GaN-based LED chip would cause additional cumbersome processing steps. On the other hand, it is well known that the external quantum efficiency of LEDs depends on the refractive index and morphology of the p-GaN layer. One possible reason for the poor external quantum efficiency is the low light extraction efficiency, due to a large total internal reflection, as predicted by Snell’s law. That is, the photons generated in the active layer for a flat p-GaN surface are trapped within the LEDs, due to the limited critical angle (∼23°) [8]. In order to overcome this issue and also enhance the ESD endurance, a two-layer p-GaN structure was demonstrated [6]. Therefore, we propose a novel method to suppress the ESD-induced damage. We have fabricated GaN-based LEDs incorporated with MOS capacitors of different MOS configurations by streamlining the fabrication process. The electrical properties of these LEDs will be characterized and discussed in detail. 2. Experiments In this experiment, InGaN/GaN multiple quantum-well (MQW) LEDs were grown on 2 inch c-face (0001) sapphire substrates using metal–organic chemical vapor deposition (MOCVD) at low pressure. For the growth of the GaN epilayers, trimethylgallium (TMGa), trimethylindium (TMIn), and ammonia (NH3 ) were used as Ga, In, and N sources, respectively. Silane (SiH4 ) and bis-cyclopentadienyl magnesium (Cp2 Mg) were used as n-type and p-type dopants, respectively. The structure consists of a 30 nm thick GaN buffer layer grown at 550 °C, a 2 µm thick undoped GaN epilayer grown at 1050 °C, a 1 µm thick Si-doped GaN epilayer, an In0.23 Ga0.77 N/GaN MQW active layer grown at 800 °C, and finally a 200 nm thick Mg-doped GaN epilayer grown at 1000 °C. The MQW active layer was made up of five periods of 3.0 nm thick InGaN well layer and 13 nm thick GaN barrier layer. The LED chips were fabricated using a standard chip-processing technique including photolithography, inductively coupled plasma (ICP) etching, electron-beam evaporation, and furnace annealing. Initially, the surface of the p-type GaN layer was partially etched until the n-type GaN layer was exposed. Next, indium tin oxide (ITO) was deposited on the p-type GaN surface as the transparent contact layer (TCL). Afterward, Ni/Pt/Au was deposited on top of the ITO-capped p-GaN and also on n-type GaN surface as p-type and n-type electrodes, respectively. The SiO2 was then deposited on the LED surface to serve as a passivation layer. Next, the wafer was lapped and polished down to about 100 µm in thickness. Finally, the wafer was cut into a rectangular shape of 300 µm × 300 µm for subsequent measurements. Note that the final chip size was about 320 µm × 320 µm due to an additional area occupied by a MOS capacitor in the mesa region. For ease of comparison in device performance, the entire luminescent area (i.e. TCL area) was deliberately kept constant for LEDs both with and without a MOS capacitor. For the MOS capacitor fabrication, different MOS configurations were designed by either extending the metal line from the p-electrode to the vicinity of the n-electrode or from the n-electrode to the p-electrode, and all of them were to be compared with a reference LED without a MOS capacitor. There are four types of MOS capacitor, as shown in Fig. 1. Fig. 2 shows the detailed schematic view of

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b

a

25

c

e

d

Fig. 1. The schematic structure of a GaN LED with and without a MOS capacitor: (a) the metal line extended from the pelectrode with a ring shape, (b) the metal line also extended from the p-electrode but with half the length compared to (a), (c) the metal line extended from the n-electrode, (d) the metal lines extended simultaneously from the p-electrode and the n-electrode, and (e) the reference sample with no MOS structure.

a

b

p-electrode

metal layer p-GaN p-AlGaN MQWs n-GaN metal layer SiO2

p-electrode n-electrode

TCL

n-GaN undoped-GaN GaN buffer layer sapphire

n-electrode oxide layer (mesa region)

Fig. 2. A schematic drawing showing (a) the fabrication procedure of an InGaN/GaN LED with a MOS capacitor and (b) the corresponding plane view of the InGaN/GaN LED with a MOS capacitor.

a typical GaN-based LED with a MOS capacitor, which is realized by extending the metal line directly from the p-type electrode to the top surface of an SiO2 -capped n-GaN layer near the vicinity of the n-type electrode. Note also that the lateral side surface of the mesa region is also covered with an SiO2 film. During the LED fabrication, the mesa region was defined by using the ICP etcher to etch the device epilayers until the n-type GaN layer was exposed in order to keep the individual LEDs isolated from one another. The ITO was then deposited on the p-type GaN surface. The Ni/Pt/Au was simultaneously deposited on the ITO-capped p-GaN surface and n-type GaN in order to serve as p-type and n-type electrodes, respectively. It should be noted that the n-electrode was connected directly to the n-GaN layer rather than the SiO2 . In order to prevent moisture from degrading the

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device performance, an SiO2 film serving as the passivation layer was deposited by plasma-enhanced chemical vapor deposition (PECVD) to cover the surfaces of the TCL and mesa region. In addition, the foregoing SiO2 and n-GaN layers also functioned as the respective oxide and semiconductor layers of the MOS capacitor structure. The Ni/Pt/Au or Ti/Al was then deposited over the SiO2 -capped mesa region to complete the remaining metal portion of the MOS capacitor. On the other hand, different oxide thicknesses were deposited on the top of the exposed n-GaN epilayer as the oxide layer of the MOS capacitor. The various oxide thicknesses implemented were 300, 500 and 700 Å. Next, the ESD endurance test was executed using a Model 910 Electro-tech ESD simulator system to characterize these samples. In this study, we applied negative ESD bias to the LED with an increment of 50 V of human body mode (HBM) which has a charging time of 0.5 s. After an ESD stress, the leakage current was measured at 5 V reverse bias applied to the LEDs. Whenever the measured leakage current of a DUT (device under test) was larger than 2 µA, the device was then considered operating in a failure state due to the junction damage. To assess the level of ESD-induced damage, an optical microscope was used to evaluate the extent of device failure. 3. Results and discussion Fig. 1 reveals three different MOS configurations along with a reference sample used in this experiment. In Fig. 1(a), the metal layer of the MOS capacitor was directly extended from the ptype electrode to the vicinity of the n-type electrode via the top surface of the SiO2 passivation layer functioning as the oxide layer of the MOS capacitor. As shown in Fig. 1(b), the metal layer of the MOS capacitor was also extended from the p-type electrode, but with only half the length compared to the open ring structure implemented and shown in Fig. 1(a). For comparison, Fig. 1(c) depicts the device with the metal layer extended instead from the n-type electrode to the proximity of the p-type electrode. On the other hand, Fig. 1(d) exhibits a device with double metal lines extending simultaneously from the n-electrode and the p-electrode. Fig. 1(e) presents a reference sample without incorporating a MOS capacitor. The ESD equivalent circuit of the InGaN/GaN LED with a MOS capacitor is depicted in Fig. 3 under the HBM condition. Here, the resistances are the charging and discharging resistors, respectively, and the MOS capacitor is equivalent to a two-terminal device. The typical values for the capacitor and a discharging resistance of HBM application are 100 pF and 1.5 k, respectively. First, the capacitor is charged to a desired ESD voltage through the charging resistance and it is then discharged to a DUT via a discharging resistance. The ESD test model for an LED with a MOS capacitor is depicted in Fig. 4. Under a positive ESD stress operation, the injection current tends to flow across the LED from p-GaN to n-GaN through the MQW layer, as shown in Fig. 4(a). Fig. 4(a) presents the schematic LED with a MOS capacitor, where the flowing direction of injection current is indicated. The dotted line indicates that the current flow circulated between the n-GaN and the electrode rather than going through the SiO2 . On the other hand, when a negative ESD stress was applied, the metal line of the MOS capacitor connected to the p-electrode of the LED was induced with a negative charge as the current was injected from the n-GaN layer shown in Fig. 4(b). According to Fig. 4(b), the direction of injection current is depicted as the solid arrow line running from the n-electrode to the p-electrode through the oxide layer. As the electric field induced became high enough, this MOS capacitor could break down by puncturing through its oxide layer. Consequently, the ESD stress current could then be guided to the p-electrode via the metal line of MOS capacitor. Thus, our proposed design could effectively protect the LED from potential ESD stress impact. On the other hand, when the metal line of the MOS capacitor is connected instead to the n-GaN layer, as indicated with a solid and dotted arrow line shown in Fig. 4(c), during a negative ESD stress operation the injection current could flow from the n-GaN layer and through the metal line of the MOS capacitor, and finally penetrate through the MQW layer, resulting in LED damage. The usefulness of this structure is therefore very limited when providing the necessary ESD protection in an actual operation. Since the injection current could easily flow across the p–n junction if a positive ESD voltage stress was applied, the focus of our study was therefore concentrated on using the negative ESD stress instead for the planned experiments. Hence, a negative ESD stress was applied to the anode while keeping the cathode grounded. The measured ESD data (the percentage of device yield that passed

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Ω

Ω

Fig. 3. The ESD equivalent circuit of an InGaN/GaN LED with a MOS capacitor.

a

b p-electrode

p-electrode

p-GaN p-AlGaN MQWs

Puncture through

n-electrode

n-GaN

p-GaN p-AlGaN MQWs n-GaN

n-electrode

metal layer

metal layer SiO2

SiO2

n-GaN

n-GaN

undoped-GaN

undoped-GaN

GaN buffer layer sapphire

GaN buffer layer sapphire

c p-electrode

p-GaN p-AlGaN MQWs n-GaN metal layer SiO2

n-GaN undoped-GaN GaN buffer layer sapphire

Fig. 4. The ESD endurance test model of the LED: (a) under a positive ESD stress operation, (b) under a negative ESD stress operation with a metal line extended from the p-electrode, and (c) under a negative ESD stress operation with a metal line extended from the n-electrode.

the test) for an LED with and without a MOS capacitor are shown in Fig. 5. Fig. 6 shows the ESD performance of sample A in response to different oxide thicknesses of MOS capacitor implemented. In this experiment, all the ESD-stressed samples (A to D) and reference samples, consisting of 20 pieces each, were used. Several facts were learned immediately after analyzing the results shown in Figs. 5 and 6. First, it was found that the ESD tolerability of sample A was the highest among all LED batches tested, indicating that a proper metal layer design did help to alleviate the adverse effect of ESDinduced current distribution. The LED with a MOS capacitor (i.e. sample A) withstood an ESD voltage of 1500 V compared to that of the LED without a MOS capacitor, which endured only up to 450 V. The average negative ESD voltages withstood were about 1075 V and 385 V for LEDs with and without a MOS capacitor, respectively. Second, increasing the SiO2 thickness did not noticeably improve the ESD

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100

Sample A Sample B Sample C Sample D Reference

Pass Yield (%)

80

60

40

20

0 200

400

600

800

1000

1200

1400

1600

Reverse ESD (V)

Fig. 5. The measured ESD results as a function of stress voltage for InGaN/GaN LEDs with and without a MOS capacitor.

1600

Reverse ESD (V)

1400 1200 1000 800 600 400 200

700

500

300

Oxide layer thickness (Å)

Fig. 6. A box diagram showing the measured ESD results for the MOS capacitor with different oxide layer thicknesses.

tolerability. However, the ability to withstand ESD was slightly weaker when the thickness became thinner (i.e. 300 Å). The average negative ESD voltages found were about 1075 V, 1010 V and 970 V, corresponding to an oxide thickness of 700 Å, 500 Å and 300 Å, respectively. We believe that the relatively easy puncture of the oxide layer was in fact due to the high electric field induced. Third, the metal line extending from the n-electrode had provided virtually no benefit for ESD improvement. Fourth, it was shown that higher ESD protection could be achieved in sample A by properly routing the metal line of the MOS capacitor compared to sample B. The current–voltage (I–V ) characteristics of the LED before and after the ESD endurance test are shown in Fig. 7. In Fig. 7(a), the ESD voltage withstood (HBM) was about 2000 V. After an ESD stress, it was found that the leakage current was estimated to be about 0.03 µA at a reverse bias of 5 V. The leakage current was increased with increasing applied voltage. This indicates that more damage in the depletion region was generated on increasing the ESD testing times. At high bias levels (Vf > 2.2 V), the I–V characteristics were almost the same due to the high series resistance. On the other hand, the failure state of the LED after ESD stress is also presented in Fig. 7(b). It is obvious that the leakage current was larger than 2 µA and the ESD voltage was about 400 V. Fig. 8 shows the relevant photographs of LEDs with and without a MOS capacitor taken after the ESD evaluation measurements. It was clearly demonstrated that burning spots were randomly distributed over the TCL surface and the MOS capacitor. In fact, the burning spots were primarily situated in the region of the MOS capacitor, and as the ESD stress frequency increased, the spots eventually spread

P.C. Tsai et al. / Superlattices and Microstructures 48 (2010) 23–30

a

1

b before ESD test after ESD test

0.01 1E-3

Forware & reverse current (A)

Forware & reverse current (A)

0.1

1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10

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1 0.1 0.01 1E-3 before ESD test after ESD test

1E-4 1E-5 1E-6 1E-7 1E-8 1E-9 1E-10 1E-11

1E-11

1E-12 -15

-10

-5

0

5

-15

-10

-5

0

5

Applied voltage (V)

Applied voltage (V)

Fig. 7. The I–V characteristics of the LED before and after ESD stress for (a) the pass state and (b) the failure state.

a

b

Fig. 8. Photographs showing the extent of ESD-induced damage on LEDs (a) with and (b) without an additional MOS capacitor.

out in a sporadic fashion over the surface of TCL. We believe there are two reasons which could explain our findings. First, we speculate that the injection current is mainly concentrated on the MOS capacitor during the initial phase of negative ESD stressing, and as the MOS capacitor eventually fails to operate, the injection current is then diverted to the TCL surface. As already mentioned in the early part of this article, the MOS capacitor was deemed to have failed because of the junction damage when the LED leakage current measured immediately after ESD stressing at a reverse bias voltage of −5 V was larger than 2 µA. In other words, the presence of a MOS capacitor effectively helps to bypass the ESD stress from going through the LED directly. However, as the magnitude of the ESD-induced current flowing through the MOS capacitor increases, the oxide layer eventually becomes punctured as a result of the oxide breakdown. Consequently, burning spots are thereby generated over the surface of the MOS capacitor and the resulting current then flows through InGaN/GaN LED directly after the breakdown of the MOS capacitor has taken place. Second, since the MOS capacitor functions as a two-terminal device, then, when the MOS capacitor is connected in parallel with a discharged capacitor shown in Fig. 3, the very arrangement leads to an enhancement in the total capacitance (CMOS + Cdischarged ). Hence, the effective time constant (RC ) increases as a result of higher capacitance. The measurement results indicated that our proposed device scheme could maximize the capability of a MOS capacitorguarded InGaN/GaN LED against ESD-induced damage. Thus, without sacrificing the output power, a much larger ESD tolerability could be achieved by connecting the LED in parallel with a MOS capacitor.

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4. Conclusions We have demonstrated the high ESD endurance capability of InGaN/GaN LEDs by incorporating an additional MOS capacitor. The MOS capacitors implemented have different routing designs. It was found that a relatively higher ESD protection could be achieved by extending the metal line from the pelectrode. When connecting a MOS capacitor in parallel with the InGaN/GaN LED, the resulting device scheme could significantly increase the ESD robustness from 385 to 1075 V in HBM and virtually no degradation in the light extraction efficiency was observed. The enhancement in the ESD tolerability could also be further obtained through an increase in the equivalent capacitance of the MOS capacitor by improving the material quality of the corresponding SiO2 layer. Acknowledgements This work was conducted in part at the Advanced Optoelectronic Technology Center (AOTC) of National Cheng Kung University; all of the equipment access and technical support provided by the AOTC is therefore greatly appreciated. References [1] [2] [3] [4] [5] [6]

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