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Four-chip hybrid carrier holds down system costs
World Abstracts on Microelectronics and Reliability Optimum policies when preventive maintenance is imperfect. TOSHIO NAKAGAWA. IEEE Trans. Reliab. R-28, (4) 331 (October 1979). This paper considers three models with imperfect preventive maintenance (pro), viz the unit after pm is not always like new; i) the unit is repaired upon
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failure, ii) the unit undergoes minimal repair at failure, and iii) the failed unit is detected only by perfect pro. Optimum preventive maintenance policies minimizing the s-expected cost rate for each model are discussed.
4. MICROELECTRONICS GENERAL VHSIC finally gets untracked. RAY CONNOLLY. Electronics p. 81 (3 January 1980). Six-year $210 million program gets over congressional hurdle with first nine contracts of Phase Zero to be.awarded this month. Chip market overestimated, says IT]'. HARVEYJ. H1NDIN. Electronics p. 90 (3 January 1980). One of the biggest potential customers calls maker's figures "incredibly exaggerated" even under ideal conditions. The new microelectronic processing technology: a review of the stute-of-the-art. R. L. MADDOX. Microelectron. J. I1, (1) 4 (1980). This paper discusses advances in the lithographic process. Emphasis will be on resist modelling, developing, and removal methods. Next, the various dry etching techniques are presented. The rest of the paper discusses processing advances outside the category of dry processing. This includes lift-off patterning, ion implantation techniques, laser annealing, RF annealing, and plasma deposition. CMOS, present and future. TOSHIO ABE. Microelectron. J. 10, (4) 31 (1979). Today, Complementary Metal-OxideSemiconductor (CMOS) technology is recognised as one of the more important semiconductor technologies, a situation which was not envisaged when it was first introduced. In this article, the present status and future trend of the technology and applications of CMOS LSI, will be surveyed, referring mainly to the situation in Japan. Future microelectronic devices: materials aspects and interfacial phenomena. L. E. MYRa. Microelectron. J. 10, (4) 12 (1979). The inevitable, continued reduction in dimensional features of microelectronic devices has already caused a shift to higher-resolution processing techniques and will require even more sophisticated circuit viewing schemes
involving the transmission electron microscope. Decreasing dimensions of all components will result in new equivalent circuit concepts because interfaces normally swamped in LSI devices, will become viable, controllable fe.atures of fabrication, and may in fact be the device limiting dimensional feature. Furthermore, the ability to tailor lattice parameters and stoichiometries over small dimensions (<0.01/~m) will, coupled with phenomena at the submicron level, pose some of the most exciting materials applications of the century.
Appfications of auger and photoelectron spectroscopy in characterizing IC materials. R. K. LowRY and A. W. HOGREFE. Solid-St. Technol. p. 71 (January 1980). Modern surface analysis equipment is well suited to characterizi.ng the thin-film structures of microelectronic devices. In-situ microbeam examination of films and interfaces of devices has become a valuable R&D and problem solving tool for the manufacturer of integrated circuits. Several relatively simple thin-film analyses which helped improve IC production processing are discussed. Topics include wire bonded interfaces, effect of plasma processing on surfaces, metallization adherence, etching of metal films, diffusion damage, and surface characterization of silicon materials. Taking the heat OFFsemiconductor temperature testing. WILLIAMMARK. Electronics p. 161 (14 February 1980) Probes make measurements easy, but for accuracy the user must understand the thermal characteristics of sensors and devices. IC makers ponder polysilicon shortage predicted by year's eud. LARRYWALLER.Electronics p. 45 (14 February 1980). Demand may exceed supply as early as August; some observers disagree, but supply is seen as tight.
5. MICROELECTRONICS DESIGN AND CONSTRUCTION Four-chip hybrid carrier holds down system costs. DA~ I. AMEYand JACK W. BALDE. Electronics p. 113 (17 January 1980). An analysis of packaging options settles on four-chip hybrids for small-scale-integrated portion of central processor. A quick method for calculating temperatures arising from the rear cooled heat source geometries found in microelectronics. D. J. D~,~. Proc. lnternepcon UK '79 p. 202, Brighton (16-18 October 1979). Many temperature distribution problems in microelectronics are of the general form of heat generators located on one surface of a thin substrate which has a heat sink mounted upon its rear face. In these cases it is usually possible to assume that there is no heat loss except to the heat sink which maintains a uniform temperature over its entire surface. The analysis of such heat flow spread from some specific heat source geometries has been tackled in various papers (1-7). These analyses generally only apply to the hottest point and do not take into account multiple heat sources. The analysis by the present author (6) was based upon a fixed angle solution for the heat flow into a semi-infinite
body being equated to that obtained by integration and super-position (8) and resulted in the well known 45 ° model. Subsequent to this analysis it was found that the evaluation of temperature arising from long strip heat sources was not amenable to this approach. A new general technique has therefore been developed for all problems of this type. This new technique relies upon the principles of super-position (8) and reflected heat sources (9, 10) where planes of symmetry represent insulated boundaries and planes of inverted symmetry heat sink. The detailed mathematical analysis of the particular case of a long strip source is given in an AWRE Report 042/79 available from HMSO (9). This paper discusses the technique and its application to all rear sunk geometries. ILPOS----a programme system for the computer-aided coarse layout design of l'L-circuits. M. GIESELER.Nachrichtentechnik-Elektronik 29, (12) 500 (1979) (in German). It is dealt with an algorithm which enables the computerassisted design of IZL-layouts, in particular the arrangement of the transistors, connecting lines and contact windows according to the predetermined electric wiring
545
failure, ii) the unit undergoes minimal repair at failure, and iii) the failed unit is detected only by perfect pro. Optimum preventive maintenance policies minimizing the s-expected cost rate for each model are discussed.
4. MICROELECTRONICS GENERAL VHSIC finally gets untracked. RAY CONNOLLY. Electronics p. 81 (3 January 1980). Six-year $210 million program gets over congressional hurdle with first nine contracts of Phase Zero to be.awarded this month. Chip market overestimated, says IT]'. HARVEYJ. H1NDIN. Electronics p. 90 (3 January 1980). One of the biggest potential customers calls maker's figures "incredibly exaggerated" even under ideal conditions. The new microelectronic processing technology: a review of the stute-of-the-art. R. L. MADDOX. Microelectron. J. I1, (1) 4 (1980). This paper discusses advances in the lithographic process. Emphasis will be on resist modelling, developing, and removal methods. Next, the various dry etching techniques are presented. The rest of the paper discusses processing advances outside the category of dry processing. This includes lift-off patterning, ion implantation techniques, laser annealing, RF annealing, and plasma deposition. CMOS, present and future. TOSHIO ABE. Microelectron. J. 10, (4) 31 (1979). Today, Complementary Metal-OxideSemiconductor (CMOS) technology is recognised as one of the more important semiconductor technologies, a situation which was not envisaged when it was first introduced. In this article, the present status and future trend of the technology and applications of CMOS LSI, will be surveyed, referring mainly to the situation in Japan. Future microelectronic devices: materials aspects and interfacial phenomena. L. E. MYRa. Microelectron. J. 10, (4) 12 (1979). The inevitable, continued reduction in dimensional features of microelectronic devices has already caused a shift to higher-resolution processing techniques and will require even more sophisticated circuit viewing schemes
involving the transmission electron microscope. Decreasing dimensions of all components will result in new equivalent circuit concepts because interfaces normally swamped in LSI devices, will become viable, controllable fe.atures of fabrication, and may in fact be the device limiting dimensional feature. Furthermore, the ability to tailor lattice parameters and stoichiometries over small dimensions (<0.01/~m) will, coupled with phenomena at the submicron level, pose some of the most exciting materials applications of the century.
Appfications of auger and photoelectron spectroscopy in characterizing IC materials. R. K. LowRY and A. W. HOGREFE. Solid-St. Technol. p. 71 (January 1980). Modern surface analysis equipment is well suited to characterizi.ng the thin-film structures of microelectronic devices. In-situ microbeam examination of films and interfaces of devices has become a valuable R&D and problem solving tool for the manufacturer of integrated circuits. Several relatively simple thin-film analyses which helped improve IC production processing are discussed. Topics include wire bonded interfaces, effect of plasma processing on surfaces, metallization adherence, etching of metal films, diffusion damage, and surface characterization of silicon materials. Taking the heat OFFsemiconductor temperature testing. WILLIAMMARK. Electronics p. 161 (14 February 1980) Probes make measurements easy, but for accuracy the user must understand the thermal characteristics of sensors and devices. IC makers ponder polysilicon shortage predicted by year's eud. LARRYWALLER.Electronics p. 45 (14 February 1980). Demand may exceed supply as early as August; some observers disagree, but supply is seen as tight.
5. MICROELECTRONICS DESIGN AND CONSTRUCTION Four-chip hybrid carrier holds down system costs. DA~ I. AMEYand JACK W. BALDE. Electronics p. 113 (17 January 1980). An analysis of packaging options settles on four-chip hybrids for small-scale-integrated portion of central processor. A quick method for calculating temperatures arising from the rear cooled heat source geometries found in microelectronics. D. J. D~,~. Proc. lnternepcon UK '79 p. 202, Brighton (16-18 October 1979). Many temperature distribution problems in microelectronics are of the general form of heat generators located on one surface of a thin substrate which has a heat sink mounted upon its rear face. In these cases it is usually possible to assume that there is no heat loss except to the heat sink which maintains a uniform temperature over its entire surface. The analysis of such heat flow spread from some specific heat source geometries has been tackled in various papers (1-7). These analyses generally only apply to the hottest point and do not take into account multiple heat sources. The analysis by the present author (6) was based upon a fixed angle solution for the heat flow into a semi-infinite
body being equated to that obtained by integration and super-position (8) and resulted in the well known 45 ° model. Subsequent to this analysis it was found that the evaluation of temperature arising from long strip heat sources was not amenable to this approach. A new general technique has therefore been developed for all problems of this type. This new technique relies upon the principles of super-position (8) and reflected heat sources (9, 10) where planes of symmetry represent insulated boundaries and planes of inverted symmetry heat sink. The detailed mathematical analysis of the particular case of a long strip source is given in an AWRE Report 042/79 available from HMSO (9). This paper discusses the technique and its application to all rear sunk geometries. ILPOS----a programme system for the computer-aided coarse layout design of l'L-circuits. M. GIESELER.Nachrichtentechnik-Elektronik 29, (12) 500 (1979) (in German). It is dealt with an algorithm which enables the computerassisted design of IZL-layouts, in particular the arrangement of the transistors, connecting lines and contact windows according to the predetermined electric wiring