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High performance and highly reliable novel CMOS devices using accumulation mode multi-gate and fully depleted SOI MOSFETs
Microelectronic Engineering 84 (2007) 2105–2108 www.elsevier.com/locate/mee
High performance and highly reliable novel CMOS devices using accumulation mode multi-gate and fully depleted SOI MOSFETs W. Cheng a,*, A. Teramoto a, R. Kuroda b, M. Hirayama a, T. Ohmi a a
New Industry Creation Hatchery Center, Tohoku University, Japan b Graduate School of Engineering, Tohoku University, Japan
Abstract In this paper, the electrical characteristics of multi-gate MOSFETs (MUGFETs) using the advanced radical gate oxide and a suppression of Negative bias temperature degradation in accumulation mode FD-SOI MOSFETs are described. Firstly, we experimentally demonstrate that the multi-gate MOSFETs using radical oxide effectively suppress the degradation of Sfactor values resulted from its superior oxidation at the sidewall. Secondly, we indicate that the device performance is dramatically improved by introducing MUGFETs device structure originated from its effective channel area. Finally, we reveal the improvement of current drivability and a suppression of Negative bias temperature instability (NBTI) in accumulation mode FD-SOI MOSFETs. Keywords: Multi-gate MOSFETs; Silicon on insulator; Accumulation mode; NBTI
1. Introduction The improvements of the current drivability and device reliability are very important for realizing the high performance CMOS circuits. It has been reported that the current drivability of p-MOSFET on Si(110) surface is much larger than that on Si(100) surface[1,2]. Multi-gate MOSFETs (MUGFET) such
Corresponding author. Tel.:+ 81 22 7953977; fax: +81 22 7953986. E-mail address:[email protected] (W. Cheng)
0167-9317/$ - see front matter Ó 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2007.04.124
as the Tri-gate FETs consist of various Si surfaces with different crystal orientations, including Si(100) and (110) surfaces, are promising device candidates for the 45nm node and beyond because of their superior short-channel-effect controllability and larger effective channel area originated from the channel area of sidewall. However, there have been very small amount of works reported on the influence of the performance of MUGFETs caused by the gate oxide formation despite of its importance of improving the MUGFETs performance and turning it into practical use. On the other hand, the works on
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W. Cheng et al. / Microelectronic Engineering 84 (2007) 2105–2108
improving the performance and reliability of FD-SOI MOSFETs by device structures have been seldom reported. In this paper, we demonstrate that the MUGFETs performance is obviously improved using Kr/O2 radical gate oxide. The current drivabilities are improved in both n- and p-MOSFETs using accumulation mode (AM) MOSFETs. Finally, we demonstrate an obvious suppression of NBTI in AM devices compared with that in conventional IM MOSFETs. 2. Experimental The p- and n-MOSFETs on SOI-Si(100) surfaces are employed for this experiment. The SOI layers doping concentrations (Nsub) for both n- and p-type are 1015, 1016, and 2x1017 cm-3. The thicknesses of SOI layers (TSOI) are 50 nm for FD-SOI and 250 nm for MUGFETs, respectively. After 5-steps room temperature cleaning [3], 7.5 nm-gate oxides are formed by the dry oxidation at 900 °C and Kr/O2 radical oxidation at 400 °C [4]. For Inversion-Mode MOSFETs, P+ and B+ ions (1.0x1016 cm-2) are implanted to gate Poly-Si layer (300 nm) for nMOSFET and p-MOSFET, respectively. For Accumulation-Mode MOSFETs, P+ and B+ ions (1.0x1016 cm-2) are implanted to gate Poly-Si layer (300 nm) for p-MOSFET and n-MOSFET, respectively. As+ and BF2+ (1.5x1015 cm-2) ions are implanted to S/D region for n-MOSFET and pMOSFET, respectively. Post metal annealing was carried out at 400oC in N2/H2=90/10 for 30 minutes.
swing value is approximation to equation (1) as: S #
1 ( C D C it ) / C ox kT ln 10 u q 1 C D / C ox
(1)
where S is the S-factor value and Cit is the interface trap capacitance. The MUGFETs with Kr/O2 radical oxide gate insulator show very good S-factor values below 70mV/dec without sidewall orientation dependence compared with conventional thermal dry oxide. We consider that the significant difference of performance in the devices with radical and thermal gate oxide is originated from the sidewalls of MUGFETs consist of various Si orientations because the very low interface trap densities about 1x1010cm-2 can be realized on Si(100), (110) and (111) oriented surfaces using radical oxide[4].
P
The effective channel area of three-dimensional device such as MUGFETs is much larger compared with conventional planar MOSFETs with the same wafer occupancy area because of the existence of sidewall channels in MUGFETs. According to the device simulation result, the wafer occupancy of MUGFETs is about 50% of that in planar CMOS devices to achieve the same current drivability and the schematic device structures are shown in Fig. 1. Fig. 2 shows the subthreshold swing (S-factor) values of MUGFETs with the Kr/O2 radical oxide and dry gate oxide. It is well known that the subthreshold
105 100
S-factor Values (mV/dec)
3. Results and discussion
Fig. 1. Schematic of the device structure of Completely Balanced Multi-gate CMOSFETs with about 50% occupancy area compared with planar MOSFETs.
L=0.8 P m W=0.5 P m 10 channels T SOI=250nm
Dry Oxide O @900 C
95
Tox=7.5nm 16 -3 N sub=1x10 cm
90 85 80
Kr/O 2
75
@400 C
p-channel SOI-FinFETs
O
70 65 60 0
<110>
15
30
45
<100>
60
75
90
105 120 135 150 165 180
<110> <100> O Channels Angles ( )
<110>
Fig. 2. S-factor characteristics of MUGFETs using radical and thermal gate oxide. The MUGFETs using Kr/O2 radical gate oxides show very good S-factor values below 70mV/dec in all channel directions and we consider the superiority using radical oxide is caused by the ideal interface state on various Si orientations of sidewall [4].
W. Cheng et al. / Microelectronic Engineering 84 (2007) 2105–2108
Fig. 3 shows the transconductance (gm) characteristics of p-channel planar FD-SOI MOSFETs and MUGFETs on Si(100) surface. The gm values of p-channel MUGFETs are improved from 1.8 times to 3.5 times varied with increasing the gate bias. It has been reported that the peak value of gm in p-MOSFETs on Si(110) surface is 1.9 times greater than that on Si(100) surface [5]. The same tendency is observed in this experiment. The gm characteristics of p-channel MUGFETs perform like that on Si(110) surface rather than that on Si(100) surface. We considered that the Si(110) oriented sidewalls in MUGFETs with radical gate oxides enhance the total performance in this experiment. -6
5.0x10
p-channel MOSFETs
2107
Si(110) surface. The current drivability of p-channel MUGFET is 2.5 times larger than that of FD-SOI p-MOSFET. It has been reported that the hole mobility on Si(110) surfaces are much larger than that on Si(100) surface [2]. In this experiment, the top side of p-channel MUGFET is on Si(100) surface and sidewalls are on Si(110) surface. The obvious improvement of the performance in MUGFETs is considered the maximize utilization of the sidewalls. Fig. 5 (a)-(d) show the schematic of inversion and accumulation mode device structures. (a) Inversionmode (IM) n-MOSFET, (b) Inversion-mode (IM) p-MOSFET, (c) Accumulation-mode (AM) n-MOSFET and (d) Accumulation-mode (AM) p-MOSFET. The off-state is realized by the depletion-layer caused by the difference of workfunctions of the gate electrode and SOI layer.
-6
Transconductance, gm (s)
4.0x10
1.8 times SOI-FinFET TSOI=250nm
-6
3.0x10
L=10Pm W=0.5Pm 10 channels Kr/O2=7.5nm 16
2.0x10
-3
n+
n+
n Iinv
p
p+
S
D
p + Iinv inv p
n+
-6
FD-SOI TSOI=50nm
1.0x10
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
Gate Voltage, Vg (V)
2.5 times
3.0x10
-4
2.5x10
Vg-Vth=0~-2.5V 1step=-0.5V
SOI-FinFET TSOI=250nm
16
-4
-3
FD-SOI TSOI=50nm
-4
1.5x10
-4
1.0x10
-5
5.0x10
0.0 -3.0
-2.5
-2.0
-1.5
-1.0
p+
-0.5
n+
D
S
n+
p+ I p p
BOX
acc
D
p+ p
BOX
p-type Si
p-type Si
Accumulation-Mode -Mode
Fig. 5. Schematic of inversion and accumulation mode device structures.
p-MOSFETs L=10Pm W=0.5Pm 10 channels Kr/O2=7.5nm Nsub=1x10 cm
2.0x10
S
acc acc
-4
3.5x10
G
(d)
n+ I n
Fig. 3. Transconductance characteristics of p-channel MUGFETs are improved from 1.8 times to 3.5 times compared with that of conventional FD-SOI MOSFETs.
-4
Inversion -Mode
(c)
-3.0
p+ p
p-type Si
p-type Si G
n
D
BOX
BOX
0.0
Drain Current, ID (A)
(b) S
Nsub=1x10 cm
3.5 times
-6
G
G
(a)
0.0
Drain Voltage, VD (V)
Fig. 4. ID-VD characteristics of p-channel MUGFETs and conventional FD-SOI MOSFETs. The current drivability of p-channel MUGFET is 2.5 times larger than that of FDSOI p-MOSFET with the same wafer area.
Fig. 4 shows ID-VD characteristics of p-channel MUGFET and FD-SOI MOSFET fabricated on
Fig. 6 shows the Idsat values of the IM(conventional) and the AM-MOSFETs as a function of Nsub on Si(100) surface. The Idsat values decrease with an increasing of Nsub for both the conventional IM n- and p-MOSFETs. However, the Idsat values increase with an increasing of Nsub for both the AM n- and p-MOSFETs. The Idsat values are 1.08mA, 1.11mA, 1.19mA in AM n-MOSFETs and 0.31mA, 0.32mA, 0.36mA in AM p-MOSFETs with Nsub of 1015, 1016, and 2x1017 cm-3, respectively. Ioff values are blew 1x10-11A in these MOSFETs. It is observed that the stronger Eeff dependence of mobility, the greater improvement of Idsat is realized because the mobilities at AM devices are mainly improved by the effects of the reduction of Eeff at the same gate bias and bulk current on high doping substrates.
W. Cheng et al. / Microelectronic Engineering 84 (2007) 2105–2108
Fig. 7 (a) shows the schematic cross sectional view of the experimental setup and (b) shows the energy band diagram of IM and AM p-channel MOSFETs in the NBTI stress acceleration measurement. It is suggested that for a same bias and temperature condition, energy level of holes, on which degradation due to NBTI stress strongly depends, is lower for AM devices compared to IM devices [6,7].
Threshold Voltage Shift, 'Vth[mV]
2108
10
Stressed@413[K] Eox=5.3MV/cm 16 -3 Nsub=1x10 cm
Inversion mode
1
0.1
Accumulation mode 1
10
2
10
3
10
4
10
Stress Time [sec]
Fig. 8. NBTI-induced Vth shift in IM and AM p-MOSFETs.
Drain Saturation Current, IDsat (mA)
A ccum ulation-m ode n-MO SFETs
Si(100) FD-SOI MOSFETs
4. Conclusions
L/W=10/20 P m Inversion-m ode Tox=7.5nm n-MO SFETs T SOI/T BOX =50/100nm
Accum ulation-m ode p-MO SFETs
V G -V th =2.5V
V D =3V
Inversion-m ode p-MO SFETs
-3
SOI Layer Doping Concentration, N sub (cm )
Fig. 6. Idsat of MOSFETs on Si (100) surface as a function of Nsub. Idsat values increase with an increase of Nsub in AM n- and p-MOSFETs. Oxide
Oxide
-VG p+-Poly Si
We have demonstrated that the high performance and highly reliable novel CMOS devices can be realized using accumulation mode multi-gate and FD-SOI MOSFETs. MUGFETs with radical gate oxide perform much better compared with conventional thermal gate oxide its high-quality oxidation on sidewalls. An improvement of current drivabilities and an obvious suppression of NBTI are realized by introducing the accumulation device structure in this experiment because of the improved effective mobility and the lower energy level of holes. We indicate the possibility of realizing the high performance and reliable balanced CMOS using accumulation mode MUGFETs for future advanced analog/digital circuits.
n+-Poly Si
Acknowledgements P+ P+ (n-type SOI for inversion mode) SOI (p-type SOI for accumulation mode)
P+
SiO2 Hole Injection 8.5x1018 [/cm3]
(a) Setup
+++++++ + ++
++++ ++++++
p-well
n-well
Inversion mode
Accumulation mode
(b)Band diagram
Fig. 7. (a) Schematic cross sectional view of the experimental setup and (b) Energy band diagram in the NBTI stress acceleration measurement.
Fig. 8 shows the experimental result of NBTIinduced threshold voltage shift of IM and AM pMOSFETs stressed at 5.3MV/cm and 413K, as a function of stress time. It is observed that the stress time for the same Vth shift of AM p-channel MOSFET is more than one-digit longer compared with that of conventional IM p-MOSFET at the same NBTI stress condition.
This work was conducted as a part of the project under Grant-in-Aid for Specially Promoted Research (project No. 18002004), supported by Japanese Ministry of Education, Culture, Sports, Science and Technology. References [1] T. Sato, Y. Takeishi, H. Hara, Phys. Rev. B 4 (1970) 1950. [2] A. Teramoto, T. Hamada, H. Akahori, K. Nii, T. Suwa, K. Kotani, et al., IEDM 2003, 801. [3] T. Ohmi, J. Electrochem. Soc. 143 (1996) 2957. [4] T. Ohmi, M. Hirayama, A. Teramoto, J. Phys D: Appl. Phys. 39 (2006) R1-R17. [5] H. S. Momose, T. Ohguro, K. Kojima, S. Nakamura, Y. Toyoshima, IEEE TED 50 (2003) 1001. [6] R. Kuroda, K. Watanabe, A. Teramoto, M. Mifuji, T. Yamada, S. Sugawa, T. Ohmi, IEDM 2005, 717. [7] K. Watanabe, R. Kuroda, A. Teramoto, S. Sugawa, T. Ohmi, ECS Transactions 1 (2005) 147.
High performance and highly reliable novel CMOS devices using accumulation mode multi-gate and fully depleted SOI MOSFETs W. Cheng a,*, A. Teramoto a, R. Kuroda b, M. Hirayama a, T. Ohmi a a
New Industry Creation Hatchery Center, Tohoku University, Japan b Graduate School of Engineering, Tohoku University, Japan
Abstract In this paper, the electrical characteristics of multi-gate MOSFETs (MUGFETs) using the advanced radical gate oxide and a suppression of Negative bias temperature degradation in accumulation mode FD-SOI MOSFETs are described. Firstly, we experimentally demonstrate that the multi-gate MOSFETs using radical oxide effectively suppress the degradation of Sfactor values resulted from its superior oxidation at the sidewall. Secondly, we indicate that the device performance is dramatically improved by introducing MUGFETs device structure originated from its effective channel area. Finally, we reveal the improvement of current drivability and a suppression of Negative bias temperature instability (NBTI) in accumulation mode FD-SOI MOSFETs. Keywords: Multi-gate MOSFETs; Silicon on insulator; Accumulation mode; NBTI
1. Introduction The improvements of the current drivability and device reliability are very important for realizing the high performance CMOS circuits. It has been reported that the current drivability of p-MOSFET on Si(110) surface is much larger than that on Si(100) surface[1,2]. Multi-gate MOSFETs (MUGFET) such
Corresponding author. Tel.:+ 81 22 7953977; fax: +81 22 7953986. E-mail address:[email protected] (W. Cheng)
0167-9317/$ - see front matter Ó 2007 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2007.04.124
as the Tri-gate FETs consist of various Si surfaces with different crystal orientations, including Si(100) and (110) surfaces, are promising device candidates for the 45nm node and beyond because of their superior short-channel-effect controllability and larger effective channel area originated from the channel area of sidewall. However, there have been very small amount of works reported on the influence of the performance of MUGFETs caused by the gate oxide formation despite of its importance of improving the MUGFETs performance and turning it into practical use. On the other hand, the works on
2106
W. Cheng et al. / Microelectronic Engineering 84 (2007) 2105–2108
improving the performance and reliability of FD-SOI MOSFETs by device structures have been seldom reported. In this paper, we demonstrate that the MUGFETs performance is obviously improved using Kr/O2 radical gate oxide. The current drivabilities are improved in both n- and p-MOSFETs using accumulation mode (AM) MOSFETs. Finally, we demonstrate an obvious suppression of NBTI in AM devices compared with that in conventional IM MOSFETs. 2. Experimental The p- and n-MOSFETs on SOI-Si(100) surfaces are employed for this experiment. The SOI layers doping concentrations (Nsub) for both n- and p-type are 1015, 1016, and 2x1017 cm-3. The thicknesses of SOI layers (TSOI) are 50 nm for FD-SOI and 250 nm for MUGFETs, respectively. After 5-steps room temperature cleaning [3], 7.5 nm-gate oxides are formed by the dry oxidation at 900 °C and Kr/O2 radical oxidation at 400 °C [4]. For Inversion-Mode MOSFETs, P+ and B+ ions (1.0x1016 cm-2) are implanted to gate Poly-Si layer (300 nm) for nMOSFET and p-MOSFET, respectively. For Accumulation-Mode MOSFETs, P+ and B+ ions (1.0x1016 cm-2) are implanted to gate Poly-Si layer (300 nm) for p-MOSFET and n-MOSFET, respectively. As+ and BF2+ (1.5x1015 cm-2) ions are implanted to S/D region for n-MOSFET and pMOSFET, respectively. Post metal annealing was carried out at 400oC in N2/H2=90/10 for 30 minutes.
swing value is approximation to equation (1) as: S #
1 ( C D C it ) / C ox kT ln 10 u q 1 C D / C ox
(1)
where S is the S-factor value and Cit is the interface trap capacitance. The MUGFETs with Kr/O2 radical oxide gate insulator show very good S-factor values below 70mV/dec without sidewall orientation dependence compared with conventional thermal dry oxide. We consider that the significant difference of performance in the devices with radical and thermal gate oxide is originated from the sidewalls of MUGFETs consist of various Si orientations because the very low interface trap densities about 1x1010cm-2 can be realized on Si(100), (110) and (111) oriented surfaces using radical oxide[4].
P
The effective channel area of three-dimensional device such as MUGFETs is much larger compared with conventional planar MOSFETs with the same wafer occupancy area because of the existence of sidewall channels in MUGFETs. According to the device simulation result, the wafer occupancy of MUGFETs is about 50% of that in planar CMOS devices to achieve the same current drivability and the schematic device structures are shown in Fig. 1. Fig. 2 shows the subthreshold swing (S-factor) values of MUGFETs with the Kr/O2 radical oxide and dry gate oxide. It is well known that the subthreshold
105 100
S-factor Values (mV/dec)
3. Results and discussion
Fig. 1. Schematic of the device structure of Completely Balanced Multi-gate CMOSFETs with about 50% occupancy area compared with planar MOSFETs.
L=0.8 P m W=0.5 P m 10 channels T SOI=250nm
Dry Oxide O @900 C
95
Tox=7.5nm 16 -3 N sub=1x10 cm
90 85 80
Kr/O 2
75
@400 C
p-channel SOI-FinFETs
O
70 65 60 0
<110>
15
30
45
<100>
60
75
90
105 120 135 150 165 180
<110> <100> O Channels Angles ( )
<110>
Fig. 2. S-factor characteristics of MUGFETs using radical and thermal gate oxide. The MUGFETs using Kr/O2 radical gate oxides show very good S-factor values below 70mV/dec in all channel directions and we consider the superiority using radical oxide is caused by the ideal interface state on various Si orientations of sidewall [4].
W. Cheng et al. / Microelectronic Engineering 84 (2007) 2105–2108
Fig. 3 shows the transconductance (gm) characteristics of p-channel planar FD-SOI MOSFETs and MUGFETs on Si(100) surface. The gm values of p-channel MUGFETs are improved from 1.8 times to 3.5 times varied with increasing the gate bias. It has been reported that the peak value of gm in p-MOSFETs on Si(110) surface is 1.9 times greater than that on Si(100) surface [5]. The same tendency is observed in this experiment. The gm characteristics of p-channel MUGFETs perform like that on Si(110) surface rather than that on Si(100) surface. We considered that the Si(110) oriented sidewalls in MUGFETs with radical gate oxides enhance the total performance in this experiment. -6
5.0x10
p-channel MOSFETs
2107
Si(110) surface. The current drivability of p-channel MUGFET is 2.5 times larger than that of FD-SOI p-MOSFET. It has been reported that the hole mobility on Si(110) surfaces are much larger than that on Si(100) surface [2]. In this experiment, the top side of p-channel MUGFET is on Si(100) surface and sidewalls are on Si(110) surface. The obvious improvement of the performance in MUGFETs is considered the maximize utilization of the sidewalls. Fig. 5 (a)-(d) show the schematic of inversion and accumulation mode device structures. (a) Inversionmode (IM) n-MOSFET, (b) Inversion-mode (IM) p-MOSFET, (c) Accumulation-mode (AM) n-MOSFET and (d) Accumulation-mode (AM) p-MOSFET. The off-state is realized by the depletion-layer caused by the difference of workfunctions of the gate electrode and SOI layer.
-6
Transconductance, gm (s)
4.0x10
1.8 times SOI-FinFET TSOI=250nm
-6
3.0x10
L=10Pm W=0.5Pm 10 channels Kr/O2=7.5nm 16
2.0x10
-3
n+
n+
n Iinv
p
p+
S
D
p + Iinv inv p
n+
-6
FD-SOI TSOI=50nm
1.0x10
-2.5
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
Gate Voltage, Vg (V)
2.5 times
3.0x10
-4
2.5x10
Vg-Vth=0~-2.5V 1step=-0.5V
SOI-FinFET TSOI=250nm
16
-4
-3
FD-SOI TSOI=50nm
-4
1.5x10
-4
1.0x10
-5
5.0x10
0.0 -3.0
-2.5
-2.0
-1.5
-1.0
p+
-0.5
n+
D
S
n+
p+ I p p
BOX
acc
D
p+ p
BOX
p-type Si
p-type Si
Accumulation-Mode -Mode
Fig. 5. Schematic of inversion and accumulation mode device structures.
p-MOSFETs L=10Pm W=0.5Pm 10 channels Kr/O2=7.5nm Nsub=1x10 cm
2.0x10
S
acc acc
-4
3.5x10
G
(d)
n+ I n
Fig. 3. Transconductance characteristics of p-channel MUGFETs are improved from 1.8 times to 3.5 times compared with that of conventional FD-SOI MOSFETs.
-4
Inversion -Mode
(c)
-3.0
p+ p
p-type Si
p-type Si G
n
D
BOX
BOX
0.0
Drain Current, ID (A)
(b) S
Nsub=1x10 cm
3.5 times
-6
G
G
(a)
0.0
Drain Voltage, VD (V)
Fig. 4. ID-VD characteristics of p-channel MUGFETs and conventional FD-SOI MOSFETs. The current drivability of p-channel MUGFET is 2.5 times larger than that of FDSOI p-MOSFET with the same wafer area.
Fig. 4 shows ID-VD characteristics of p-channel MUGFET and FD-SOI MOSFET fabricated on
Fig. 6 shows the Idsat values of the IM(conventional) and the AM-MOSFETs as a function of Nsub on Si(100) surface. The Idsat values decrease with an increasing of Nsub for both the conventional IM n- and p-MOSFETs. However, the Idsat values increase with an increasing of Nsub for both the AM n- and p-MOSFETs. The Idsat values are 1.08mA, 1.11mA, 1.19mA in AM n-MOSFETs and 0.31mA, 0.32mA, 0.36mA in AM p-MOSFETs with Nsub of 1015, 1016, and 2x1017 cm-3, respectively. Ioff values are blew 1x10-11A in these MOSFETs. It is observed that the stronger Eeff dependence of mobility, the greater improvement of Idsat is realized because the mobilities at AM devices are mainly improved by the effects of the reduction of Eeff at the same gate bias and bulk current on high doping substrates.
W. Cheng et al. / Microelectronic Engineering 84 (2007) 2105–2108
Fig. 7 (a) shows the schematic cross sectional view of the experimental setup and (b) shows the energy band diagram of IM and AM p-channel MOSFETs in the NBTI stress acceleration measurement. It is suggested that for a same bias and temperature condition, energy level of holes, on which degradation due to NBTI stress strongly depends, is lower for AM devices compared to IM devices [6,7].
Threshold Voltage Shift, 'Vth[mV]
2108
10
Stressed@413[K] Eox=5.3MV/cm 16 -3 Nsub=1x10 cm
Inversion mode
1
0.1
Accumulation mode 1
10
2
10
3
10
4
10
Stress Time [sec]
Fig. 8. NBTI-induced Vth shift in IM and AM p-MOSFETs.
Drain Saturation Current, IDsat (mA)
A ccum ulation-m ode n-MO SFETs
Si(100) FD-SOI MOSFETs
4. Conclusions
L/W=10/20 P m Inversion-m ode Tox=7.5nm n-MO SFETs T SOI/T BOX =50/100nm
Accum ulation-m ode p-MO SFETs
V G -V th =2.5V
V D =3V
Inversion-m ode p-MO SFETs
-3
SOI Layer Doping Concentration, N sub (cm )
Fig. 6. Idsat of MOSFETs on Si (100) surface as a function of Nsub. Idsat values increase with an increase of Nsub in AM n- and p-MOSFETs. Oxide
Oxide
-VG p+-Poly Si
We have demonstrated that the high performance and highly reliable novel CMOS devices can be realized using accumulation mode multi-gate and FD-SOI MOSFETs. MUGFETs with radical gate oxide perform much better compared with conventional thermal gate oxide its high-quality oxidation on sidewalls. An improvement of current drivabilities and an obvious suppression of NBTI are realized by introducing the accumulation device structure in this experiment because of the improved effective mobility and the lower energy level of holes. We indicate the possibility of realizing the high performance and reliable balanced CMOS using accumulation mode MUGFETs for future advanced analog/digital circuits.
n+-Poly Si
Acknowledgements P+ P+ (n-type SOI for inversion mode) SOI (p-type SOI for accumulation mode)
P+
SiO2 Hole Injection 8.5x1018 [/cm3]
(a) Setup
+++++++ + ++
++++ ++++++
p-well
n-well
Inversion mode
Accumulation mode
(b)Band diagram
Fig. 7. (a) Schematic cross sectional view of the experimental setup and (b) Energy band diagram in the NBTI stress acceleration measurement.
Fig. 8 shows the experimental result of NBTIinduced threshold voltage shift of IM and AM pMOSFETs stressed at 5.3MV/cm and 413K, as a function of stress time. It is observed that the stress time for the same Vth shift of AM p-channel MOSFET is more than one-digit longer compared with that of conventional IM p-MOSFET at the same NBTI stress condition.
This work was conducted as a part of the project under Grant-in-Aid for Specially Promoted Research (project No. 18002004), supported by Japanese Ministry of Education, Culture, Sports, Science and Technology. References [1] T. Sato, Y. Takeishi, H. Hara, Phys. Rev. B 4 (1970) 1950. [2] A. Teramoto, T. Hamada, H. Akahori, K. Nii, T. Suwa, K. Kotani, et al., IEDM 2003, 801. [3] T. Ohmi, J. Electrochem. Soc. 143 (1996) 2957. [4] T. Ohmi, M. Hirayama, A. Teramoto, J. Phys D: Appl. Phys. 39 (2006) R1-R17. [5] H. S. Momose, T. Ohguro, K. Kojima, S. Nakamura, Y. Toyoshima, IEEE TED 50 (2003) 1001. [6] R. Kuroda, K. Watanabe, A. Teramoto, M. Mifuji, T. Yamada, S. Sugawa, T. Ohmi, IEDM 2005, 717. [7] K. Watanabe, R. Kuroda, A. Teramoto, S. Sugawa, T. Ohmi, ECS Transactions 1 (2005) 147.