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Influence of the lightly doped drain resistance on the worst-case hot-carrier stress condition for NMOS devices
Microelectronics Reliability 41 (2001) 649±660
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In¯uence of the lightly doped drain resistance on the worst-case hot-carrier stress condition for NMOS devices Everett E. King a, Ronald C. Lacoe a,*, Janet Wang-Ratkovic a,b a
The Aerospace Corporation, P.O. Box 92957-M2/244, Los Angeles, CA 90009-2957, USA b AMD, P.O. Box 3453, Sunnyvale, CA 94088-3453, USA Received 12 September 2000; received in revised form 29 December 2000
Abstract In this paper the underlying mechanisms that produce the cross-over in worst-case hot-carrier stress condition observed at room temperature in some deep submicron lightly doped drain (LDD) NMOS devices and at cryogenic temperatures for devices with longer channel lengths are investigated. Experiments were performed that demonstrate the generality of the cross-over. The role of stress temperature, measurement temperature and stress condition were experimentally addressed. The temperature dependence of the mobility was measured, and an analysis is presented that shows that mobility changes alone do not explain the observed changes in the transconductance. A model is proposed that allows for changes in the source±drain resistance with stress time. It is suggested that the origin of the timedependent increasing source±drain resistance is the injection of charge, either in the form of ®xed charge or as interface states, into the spacer oxide above the LDD region. This model is used to explain the qualitative dependence of the worst-case stress condition on channel length and temperature. Finally, it is suggested that the methodology used to design the LDD structure be modi®ed to account for these new observations. Ó 2001 Elsevier Science Ltd. All rights reserved.
1. Introduction Recently, Wang-Ratkovic et al. [1] presented a paper, which discussed the eect of cryogenic temperatures on the hot-carrier reliability of lightly doped drain (LDD) N-channel metal oxide semiconductor ®eld eect transistors (MOSFETs). Among the ®ndings they presented were that the worst-case hot-carrier stress condition was a function of both temperature and channel length. Two dierent stress conditions were investigated: (1) the stress condition associated with the classical room temperature substrate current model which predicts that the worst-case degradation occurs at a gate voltage corresponding to the maximum substrate current, VGS @Ib max or VGS 1=2 VDS , for which the device degradation is dominated by the formation of interface states; and (2) the maximum gate voltage stress, VGS VDS , that is
*
Corresponding author. Tel.: +1-310-336-0118; fax: +1-310336-5846. E-mail address: [email protected] (R.C. Lacoe).
normally associated with maximum gate current which results in electron injection into the oxide over the drain region of the device. Speci®cally, they found for the speci®c CMOS process tested that at cryogenic temperatures (78 and 125 K) the worst-case DC stress condition shifted from VGS @Ib max for channel lengths greater than 2 lm to VGS VDS for channel lengths less than 2 lm. For 2 lm channel length devices, they found a cross-over with stress time and drain voltage in the worst-case bias condition. Furthermore, the authors extended these results to produce a qualitative guide for predicting the worst-case stress condition over a broad range of temperatures and channel lengths. Among their conclusions was that even at room temperature, as devices scaled into the deep submicron regime, VGS VDS could become the worst-case hot-carrier stress condition. Li et al. [2] have recently observed that VGS VDS is the worst-case hot-carrier stress condition in NMOS devices with channel lengths below 0.25 lm. They attribute the cross-over in worst-case bias condition to a broadening of the substrate current versus gate voltage characteristics of devices as channel length is decreased.
0026-2714/01/$ - see front matter Ó 2001 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 0 1 ) 0 0 0 0 7 - 5
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In this paper, we present new data on the room temperature hot-carrier degradation characteristics of a 0.25 lm LDD NMOS technology and ®nd that the worstcase bias condition corresponds to VGS VDS for large VDS , but as VDS decreases, the ratio of the degradation associated with a VGS VDS stress to a VGS @Ib max stress decreases. In addition, we present cryogenic hot-carrier stress data on two dierent CMOS processes which indicate that the above described cross-over in worst-case bias condition at cryogenic temperatures is a general property of LDD NMOS devices and is not speci®c to the particular CMOS process previously examined. Previous work [1,3,4] has shown that the measured damage for a device stressed at a given temperature and then evaluated at both room temperature and at cryogenic temperatures appears much larger at cryogenic temperatures. In this paper, new experiments are presented which illustrate the role of the stress condition on this eect. The second half of the paper attempts to explain the underlying physical mechanism responsible for these results. An experiment that compares the temperature dependence of the channel mobility of a virgin device to one stressed at room temperature demonstrates that the results cannot be explained by mobility degradation alone. A model is introduced that focuses on the role of the spacer oxide in explaining these results. In this model, the eect of charge injected into the spacer oxide above the LDD region is investigated. This model is used to qualitatively explain the dependence of the worst-case bias condition on temperature and channel length, as well as why the observed decrease in transconductance for a device stressed at room temperature is much larger at cryogenic temperatures. Finally, a recommendation is made to modify the methodology used to select the optimum LDD doping during the device design phase.
2. Experimental details The hot-carrier reliability of N-channel LDD MOSFETs fabricated using ®ve commercial processes from four vendors was investigated. Minimum channel lengths for the ®ve processes were 1.2 lm (process B), 1.0 lm (process D), 0.8 lm (process C), 0.5 lm (process E), and 0.25 lm (process A). It was found that the channel width had little, if any eect on the hot-carrier degradation. Thus, devices with dierent channel widths, but with the same channel length, were used interchangeably. The nominal thickness of the gate oxide in these processes is 21.5, 20, 15, 9.4, and 4 nm, respectively. The DC hot-carrier stressing and characterization were performed automatically using the HP 4155A semiconductor parametric analyzer in combination with
an HP BASIC test program. The program applied the user speci®ed stress voltages to the gate and drain of the device, stopping at prescribed intervals to characterize the device, and record the results. The deviceÕs linear threshold voltage (VT ) and maximum transconductance (Gm max ) were extracted from the current±voltage data and recorded. These measurements were made with the drain±source voltage set at 100 mV. All tests were conducted with the devices mounted in a Lakeshore MTD150 cryogenic dewar. The temperature at which the device was stressed and/or characterized was held constant using a Lakeshore Model 330 Autotuning temperature controller. The hot-carrier device lifetime was de®ned as the time required for a 10% degradation in the peak (maximum) linear transconductance. 3. Results In this section we present a series of new experimental results which address the role of channel length and temperature in determining the worst-case hot-carrier stress condition in LDD NMOS transistors. In Section 1, room temperature stress measurements on 0.25 lm devices will be presented which show that the worst-case stress condition is for VGS VDS . In Section 2, the role of the stress condition in two dierent LDD NMOS technologies is evaluated at cryogenic temperatures. The results are similar to those reported earlier [1], indicating that the cross-over eect with channel length at cryogenic temperatures is a general property of LDD NMOS devices. In Section 5, the dierent roles of stress temperature, stress condition, and characterization temperature are addressed. The results indicate that for devices stressed at VGS @Ib max , the decrease in hot-carrier lifetime between room temperature and 78 K is dominated by the dierence in actual damage to the device, while for devices stressed with VGS VDS , the large decrease in hot-carrier lifetime between room temperature and 78 K is associated with the observation that a small amount of damage at room temperature results in a large amount of apparent degradation at 78 K. 3.1. Room temperature stress measurements Figs. 1 and 2 show the Gm max degradation versus stress time at room temperature for short channel MOSFETs of 0.25 lm length fabricated using process A under stress conditions of VGS VDS and VGS @Ib max for VDS 4 and 3.3 V, respectively. For both the VDS 4 and 3.3 V stress conditions, contrary to the normal classical model where the VGS @Ib max stress condition is the worst case over the entire stress time domain, the VGS VDS is the worst-case stress condition for the ini-
E.E. King et al. / Microelectronics Reliability 41 (2001) 649±660
Fig. 1. Decrease in the normalized transconductance versus stress time at room temperature for L 0:25 lm devices for both VGS VDS and VGS @Ib max stress conditions with VDS 4 V.
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Fig. 3. Lifetime versus 1/VDS at room temperature for L 0:25 lm devices for both VGS VDS and VGS @Ib max stress conditions.
will depend on the lifetime criteria chosen. Extrapolating to determine the maximum DC voltage that will allow 10 years lifetime, one ®nds that for VGS VDS the maximum source±drain voltage is 2.13 V, while for the VGS @Ib max stress condition it is 2.25 V. The change in threshold voltage as a function of stress time for both stress conditions for a 0.25 lm MOSFET stressed at VDS 3:3 V is shown in Fig. 4. Unlike what was observed previously [1] and what was observed for the longer channel length MOSFETs in this study, there is a dramatic change in VT with hot-carrier stress. Both bias conditions degrade with similar temporal exponents and the degradation is slightly worse for the VGS @Ib max stress condition for long stress times.
Fig. 2. Decrease in the normalized transconductance versus stress time at room temperature for L 0:25 lm devices for both VGS VDS and VGS @Ib max stress conditions with VDS 3:3 V.
tial portion of the degradation curve. Since the slopes of the VGS VGD curves are less than that of the VGS @Ib max curves, the two curves eventually intersect. For both drain voltages, this intersection occurs near the lifetime criteria of a change in the normalized Gm max of 10%. Fig. 3 shows the lifetime (s) versus the inverse supply voltage (1/VDS ) at room temperature for the 0.25 lm MOSFETs. This plot includes additional stress data not shown in Figs. 1 and 2. This ®gure clearly shows that the worst-case stress condition for these transistors is the VGS VDS condition. However, since the degradation temporal exponents (Eq. (3)) are not the same, this result
Fig. 4. Decrease in the threshold voltage versus stress time at room temperature for L 0:25 lm devices for both VGS VDS and VGS @Ib max stress conditions with VDS 3:3 V.
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Fig. 5. Decrease in the normalized transconductance versus stress time at 120 K for L 1:2 lm devices for both VGS VDS and VGS @Ib max stress conditions with VDS 5 V.
Fig. 6. Lifetime versus 1/VDS at room temperature for L 1:2 lm devices for both VGS VDS and VGS @Ib max stress conditions.
3.2. Cryogenic temperature stress measurements To examine to what extent the cross-over in worstcase bias stress condition at cryogenic temperatures is general to LDD NMOS transistors, we investigated the hot-carrier stress properties of two dierent CMOS processes. In Fig. 5, the Gm max degradation versus stress time at 120 K is shown for MOSFETs with 1.2 lm channel lengths fabricated using process B (1.2 lm process) under stress conditions of VGS VDS and VGS @Ib max for VDS 5 V. The results indicate that VGS VDS is the worst-case stress condition, but that the two degradation curves have dierent temporal exponents, and will cross-over at suciently long times. The lifetime versus the inverse supply voltage at 120 K is shown in Fig. 6 for the 1.2 lm devices. Unlike for the 0.25 lm devices stressed at room temperature where the slope of the two s versus 1/VDS curves are nearly the same, the slopes for the 1.2 lm devices are suciently dierent at 125 K that the worst-case bias condition crosses over at low drain voltages. For 10 year lifetime, the worst-case stress condition is VGS @Ib max with the maximum operating voltage at 3.72 V, while for VGS VDS the maximum operating voltage is 4.01 V. These results are similar to what has been previously observed for 2 lm devices made with process D at 125 K [1]. For process C (0.8 lm process), the Gm max degradation versus stress time at 120 K for MOSFETs with 0.8 lm channel lengths under gate voltages of VGS VDS and VGS @Ib max for VDS 7 V is shown in Fig. 7. The results are qualitatively similar to those shown for the 1.2 lm device except that the lifetime is much shorter. It is interesting to note that the temporal exponents for both the process B and C transistors are nearly identical for the same stress condition. Fig. 8 shows the lifetime
Fig. 7. Decrease in the normalized transconductance versus stress time at 120 K for L 0:8 lm devices for both VGS VDS and VGS @Ib max stress conditions with VDS 7 V.
Fig. 8. Lifetime versus 1/VDS at room temperature for L 0:8 lm devices for both VGS VDS and VGS @Ib max stress conditions.
E.E. King et al. / Microelectronics Reliability 41 (2001) 649±660
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versus the inverse supply voltage at 120 K for the 0.8 lm MOSFETs. For 10 year lifetime, the worst-case stress condition is VGS @Ib max with the maximum operating voltage is 3.46 V, while for VGS VDS the maximum operating voltage is 3.60 V. 3.3. Role of stress temperature versus measurement temperature Several dierent reports [1,3,4] have commented that a given amount of hot-carrier damage has a greater impact on device characteristics at lower temperatures than at higher temperatures. To gain additional insight into the cause of this eect we conducted a series of experiments in which the eects of stress temperature, measurement temperature and bias condition were isolated. A pair of L 1 lm LDD NMOS devices from process D (a 1 lm process) were stressed at room temperature at each of the two potential worst-case stress conditions. At speci®c stress intervals, the stress was interrupted and measurements of the transconductance were made at both room temperature and at 78 K. From these data, lifetimes for devices stressed at room temperature and characterized at room temperature could be determined, as well as the lifetime for devices stressed at room temperature but characterized at 78 K. Finally, a pair of nominally identical devices were stressed at 78 K and characterized at 78 K for the same source±drain voltage (VDS 5:5 V) used for the room temperature stress measurements. The results are shown in Fig. 9. The abscissa can be understood as follows: each position is for a given set of stress temperature/characterization temperature/stress conditions. For example, 292/292/IB means the device was stressed at 292 K, characterized at 292 K, and the stress condition was VGS @Ib max . Similarly, 292/78/IB means the device was stressed at 292 K, characterized at 78 K, and the stress condition was VGS @Ib max . Finally, 78/78/IB means the device was stressed at 78 K, characterized at 78 K, and the stress condition was VGS @Ib max . VG refers to the VGS VGD bias condition. The results provide an interesting perspective on the individual roles of the three variables. For the VGS @ Ib max stress condition, the eect of lowering the characterization temperature from 292 to 78 K results in less than an order of magnitude reduction in lifetime, while actually stressing the device and characterizing the device at 78 K results in nearly a two order of magnitude further decrease in lifetime. Hence, for the VGS @Ib max stress condition, the dominant factor in accounting for the decrease in lifetime between devices stressed at room temperature and devices stressed at 78 K is the damage done by the stress, not how that damage aects device characteristics. For the VGS VDS stress condition, the eect of lowering the characterization temperature from 292 to 78 K is dramatic ± approximately a ®ve order of
Fig. 9. Hot-carrier lifetime for an L 1 lm devices as a function of stress temperature, measurement temperature and bias condition, as described in the text.
magnitude decrease in lifetime. Actually stressing the device at 78 K results in less than an order of magnitude additional decrease in lifetime. Hence, for the VGS VDS stress condition, the dominant factor in the large decrease in lifetime when comparing a device stressed at 292 and 78 K is not that more damage is done by stressing the device at 78 K, but rather that the damage caused under this stress condition has a more dramatic eect on the measured transconductance at low temperatures. From this perspective, it now becomes clear that the reason there is a change in worst-case stress condition between devices stressed at room temperature and devices stressed at cryogenic temperatures is because the type of damage which occurs from a VGS VGD stress has a much more severe eect on device parameters at cryogenic temperatures than at room temperature and not that it produces more damage in the device.
4. Discussion In this section we will begin by addressing the role of the mobility in understanding the above-presented results. By measuring the maximum transconductance as a function of temperature for both a virgin device and a stressed device, we conclude that a decrease in channel mobility due to stress cannot alone account for the observed changes in the transconductance. We then present a model which examines the role of the series source± drain resistance and its eects on the measured transconductance. In this model, the source±drain resistance is allowed to change with stress. We then present experimental evidence that demonstrates and quanti®es the change in the source±drain resistance associated with carrier freezeout at cryogenic temperatures. We suggest that in addition to freezeout, the physical mechanism
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responsible for the change in source±drain resistance at ®xed temperature is the injection of electrons into the spacer oxide above the LDD region. Since this eect is enhanced by the VGS VGD stress condition, we can explain the results shown in Fig. 9 as well as the crossover in worst-case stress condition either as temperature is lowered for ®xed channel length, or as the channel length is reduced for ®xed temperature. Finally, the model is applied to explain the previously observed [1] change in temporal exponent for devices stressed at room temperature and characterized at room temperature, 125 and 78 K. 4.1. Role of channel mobility To gain further insight into the physical mechanisms responsible for determining the worst-case stress condition for a ®xed channel length transistor, we measured the temperature dependence of a 3 lm MOSFET fabricated using process D (1 lm process). Gm max versus temperature for the virgin device is shown in Fig. 10. The experimentally derived data is compared to that predicted by the standard MOSFET equation where the mobility is derived using the temperature-dependent model presented by Watt et al. [5]. In this model, the eective mobility is limited by three scattering mechanisms: phonon scattering, Coulombic (or charge) scattering, and surface roughness scattering, 1 1 1 1 : leff lph lC lsr
1
These three scattering mechanisms can be described by the following:
Fig. 10. Transconductance versus temperature for a virgin 3 lm device (process C). The solid line is the ®t to the mobility model described in the text. The dotted line represents the expected change in transconductance if the Coulombic term in the mobility model is increased to 20%.
a 106 1 1 Eeff l2 a 1 106 3 ; l3 Eeff
1 1 leff l1
1018 ot NB Nit N z
! 1
1012 Ninv
a2
2 where Eeff is the eective transverse electric ®eld, NB is the doping concentration, Nit and Not are the densities of interface states and ®xed trapped charge in the oxide, respectively, z is the width of the inversion layer, and Ninv is the density of carriers in the inversion layer. The values of the three temperature-dependent ls and as are process independent and have been empirically determined by Cheng and Woo [6]. As can be seen in Fig. 10, the experimental Gm max versus temperature data ®t the temperature dependence of the mobility model very well. Since hot-carrier-induced degradation is caused either by interface state buildup or charge trapping in the oxide, the only expected eect on the inversion layer mobility should be an increase in the Coulombic, or charge, scattering term. For example, the change in Gm max for a 20% increase in the Coulomb scattering term is also shown in Fig. 10. In this case, the predicted change in Gm max is a decrease of about 1.6% at room temperature (295 K) and 13% at 78 K. Post-stress Gm max versus temperature data in which the decreases in Gm max at room temperature and at 78 K are similar to those that were predicted in Fig. 10, are shown in Fig. 11. The best ®t to the temperaturedependent mobility model that can be obtained by allowing only the Coulomb scattering term to change is also shown in Fig. 11. It is observed that the ®t to these post-stress data is not as good as it is for the pre-stress
Fig. 11. Transconductance versus temperature for a device stressed at room temperature. The solid line is the best ®t of the mobility model allowing for changes only in Coulombic term.
E.E. King et al. / Microelectronics Reliability 41 (2001) 649±660
Gtot t
1 Rc GF t
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1
:
6
It follows, using Eqs. (3) and (4), that the measured normalized transconductance is given by DGtot t Gtot 0 Gtot t Gtot 0 Gtot 0
Fig. 12. Equivalent circuit model for an intrinsic FET in series with the contact resistance associated with the source and drain structures.
data, suggesting that the hot-carrier-induced degradation is not totally due to a decrease in the channel mobility. 4.2. Source±drain resistance model 4.2.1. Constant source±drain resistance A simple model has been devised in order to gain insight into the mechanisms responsible for the observed device degradation as a function of temperature, channel length, and bias condition. In this model, the series resistance associated with the source and the drain regions are considered separate from the intrinsic ®eld eect transistor. This model is illustrated in Fig. 12, where the source and drain resistances are assumed equal with a value of Rc /2. Assuming a normal powerlaw degradation of the normalized transconductance with time, DGF t Atc1 b t=sc1 ; GF 0
b t=sc1 : 1 GF 0Rc 1 b t=sc1
7
Using Eq. (5), the parametric dependence of the normalized total transconductance versus time normalized to the lifetime for constant b 0:1 and c1 0:5 on the product GF (0)Rc is shown in Fig. 13. As can be seen in this ®gure, the eect of increasing Rc is to cause a parallel shift downward in the normalized transconductance versus time curve. Hence, the eect of increasing the value of the series resistance associated with the source±drain structures while assuming the intrinsic device degradation is unchanged is to increase the measured lifetime while leaving the eective temporal exponent unchanged. Physically, the above-described dependence can be understood as follows. While the eect of including a non-zero series resistance is to decrease the eective transconductance Gtot , the eect on DGtot is to decrease it even more strongly such that the normalized transconductance decreases. In fact, it can easily be shown that the lifetime sR c depends on GF (0)Rc as described by the equation sR c s 1 GF 0Rc c1 :
8
4.2.2. Time-dependent source±drain resistance We will now consider the case where the source±drain resistance is not constant, but changes as a function of
3
where GF (0) and GF (t) are the intrinsic FET transconductance before stress is applied and at time t after stress is initiated, respectively, c1 is the exponent, and s is the device lifetime de®ned by the condition DGF s b: GF 0
4
It follows that the temporal dependence of the FET transconductance can be expressed as GF t GF 01
b t=sc1 :
5
Experimentally, one does not measure the intrinsic FET transconductance, but rather a total conductance Gtot (t) consisting of the both the intrinsic FET transconductance and the conductance associated with the series resistance Rc :
Fig. 13. Normalized transconductance versus normalized time parameterized as a function of the GF Rc product for constant Rc .
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time. This could result from the injection of electrons into the spacer oxide above the source±drain LDD implant regions and/or the formation of interface states at the spacer oxide±LDD interface. Since the conductance is the inverse of the resistance, it follows that G
1 DG ) R G
DR : R
9
Assuming the source±drain resistance increases as a power law with time with lifetime sR and exponent c2 , the temporal dependence of the source±drain resistance can be described by Rc t Rc 01 b t=sR c2 :
10
De®ning C as the ratio of the resistance lifetime to the intrinsic FET lifetime, C s=sR ;
11
and
b Rc t Rc 0 1 c t=sc2 : C2
Fig. 14. Normalized transconductance versus normalized time parameterized as a function of the initial GF Rc product. In this parameterization, the source±drain resistance changes exponentially with exponent c2 0:25 and sR s:
12
Similar to the derivation of Eq. (5), it can be shown that DGtot t 1 Gtot 0
1
b t=sc1 1 GF 0Rc 0
1 GF 0Rc 01
b t=sc1
1 b : 1 c t=sc2 C2
13
To better understand the implications of Eq. (13), the normalized total transconductance versus normalized time for b 0:1, c1 0:5, c2 0:25 and sR s C 1 is plotted for dierent GF (0)Rc (0) products in Fig. 14. For Rc 0 0, the source±drain series resistance plays no role, and the results are identical to those observed in Fig. 13. At the other extreme, where GF 0Rc 0 10 and the source±drain series resistance dominates, the eective exponent for the degradation of the normalized total transconductance is that of the source±drain resistance degradation (0.25). For intermediary situations, the degradation does not follow a single exponent over the entire time domain. It can, however, be approximated by a single exponent between 0:001 6 t=s 6 1, where the value of the exponent is between 0.25 and 0.5, depending on the GF (0)Rc (0) product. The role of the value of the resistance lifetime parameter C is examined in Fig. 15. For b 0:1, GF 0Rc 0 1, c1 0:5 and c2 0:25, the eect of reducing C is to cause a parallel upward shift in the degradation curve such that the lifetime is reduced but the eective temporal exponent is unchanged. It is worth noting from Eq. (10) that the eect of changing the re-
Fig. 15. Normalized transconductance versus normalized time for ®xed c1 , c2 , GF Rc and dierent eective resistive lifetime constants.
sistance lifetime by a factor C relative to the intrinsic FET lifetime is equivalent to leaving the resistance lifetime unchanged but changing the lifetime criteria b by a factor of 1=C c2 : 4.3. Source±drain resistance measurements The series resistance of the LDD region was estimated for the 0.5 lm MOSFETs (process E) using the approach developed by Chung and Lee [7,8]. The mea-
E.E. King et al. / Microelectronics Reliability 41 (2001) 649±660
surements were made on a set of devices that had the same channel width of 11.2 lm, but channel lengths of 0.7, 1.4, 2.8, 5.6, and 11.2 lm. Gate voltage versus source±drain voltage measurements were made on this set of devices at a number of temperatures between 77 and 300 K. The source±drain series resistance was extracted for the data set obtained at each temperature following the referenced method. It was assumed that the portion of the drain±source series resistance corresponding to the leads, the source±drain contacts, and the source±drain regions behaves as a simple resistor with a constant temperature coecient. Thus, this resistance could be subtracted from the data set, leaving a resistance that should roughly correspond to the LDD resistance. The ®nal result is the resistance of the LDD region (Rc ) as a function of temperature, which is shown in Fig. 16. These results are consistent with the temperature dependence of carrier freezeout.
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Fig. 17. PISCES simulation of the decrease in the normalized transconductance versus charge deposited in spacer oxide for dierent LDD doping densities.
4.4. PISCES simulations PISCES simulations were performed to simulate the eect of and to better understand the device sensitivity to hot-carrier injected electrons that become trapped in the spacer oxide above the LDD region. In these simulations, the LDD region was 0.2 lm wide and 0.2 lm deep. Results for a 0.5 lm MOSFET are shown in Fig. 17. The decrease in Gm max is shown as a function of the amount of electron charge placed in a sheet at the surface of the LDD region, with the peak doping concentration in the LDD region as a parameter. First, it is seen that the presence of such a charge in the spacer oxide will signi®cantly degrade the transconductance. It is also shown that even a relatively small change in the peak doping concentration in the LDD region can greatly aect the amount of degradation that is observed for a given amount of ®xed charge. Clearly, the eective
Fig. 18. PISCES simulation of the change in the normalized threshold voltage.
decrease in peak doping concentration that is caused by carrier freezeout as temperature is lowered below 200 K will also signi®cantly increase the amount of degradation that occurs for this given ®xed charge in the spacer oxide. As shown in Fig. 18, the simulation also predicts changes in the threshold voltage. This result is consistent with the experimental results for an L 0:25 lm device (Fig. 4). For both the normalized transconductance and the threshold voltage, the largest eect is for the lowest doping density. This simply re¯ects that a given amount of injected charge will be a bigger percentage of the mirrored LDD charge for lower LDD doping density. 4.5. Application of the source±drain resistance model Fig. 16. Measured source±drain resistance Rc versus temperature.
In a previous study [1] the transconductance degradation versus stress time for an L 6 lm device stressed
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at 292 K at VGS @Ib max stress condition and measured at 292, 125, and 78 K was presented and is shown here in Fig. 19. We now illustrate that parameters can be chosen in the source±drain resistance model to provide a good match to the data. It was assumed that at room temperature the degradation is dominated by the intrinsic FET degradation, hence c1 0:76 was chosen and GRc 0:1 was assumed. The intrinsic FET lifetime was chosen to match the 292 K degradation curve and since the source±drain resistance changes have minimal eect at room temperature, C 1 was assumed. At 125 K, a choice of GRc 1 and c2 0:2 was made to match the experimentally determined exponent of 0.2. C was then chosen to shift the degradation curve up to intersect the data. At 78 K, c2 0:12, GRc 10 and C 0:001 yielded a good match to the data. As can be observed in Fig. 19 where the solid lines represent the predictions of the source±drain resistance model, the model is able to adequately describe the observed experimental results. While this is suggestive that the model is accurately describing the underlying physical mechanisms, it should be pointed out that the system is under constrained, and that there is more than one combination of c1 , c2 , GRc , and C which can be chosen to ®t the data. The parameters chosen to match the data indicate that the resistive lifetime is becoming very short at low temperatures. As discussed above, this re¯ects the fact that at low temperatures, due to carrier freezeout in the LDD region, a ®xed amount of trapped charge will represent a bigger percentage of the LDD charge, and hence, will have a bigger eect. Similarly, if one assumes charge is being trapped in the spacer oxide at a constant
Fig. 19. Change in normalized transconductance for an L 6 lm device stressed at 292 K at VGS @Ib max stress condition and measured at 292, 125, and 78 K [1]. The solid lines represent the prediction of the source±drain resistance model for the parameters speci®ed.
rate, the eect of carrier freezeout is that the LDD resistance increase will occur more rapidly and hence the resistance lifetime will be shorter. An additional mechanism that would also result in an upward shift of the damage curve is that the eect of interface charge on the channel mobility is more pronounced at low temperatures. 4.6. Worst-case stress condition dependence on L and T Within the above established framework of the role of the source±drain resistance and channel mobility on the hot-carrier degradation, it now becomes possible to explain the observed dependence of the worst-case stress condition on temperature and channel length as qualitatively described in Fig. 20. Let us begin by explaining the role of temperature by examining, for example, the eect of temperature on an L 1 lm device. At room temperature when the device is stressed at VGS @Ib max , the stress condition favors the formation of interface states near the drain and an associated decrease in the channel mobility. This results in a decrease in transconductance. An NMOS LDD device is ordinarily designed such that the source±drain resistance is large enough to reduce the maximum channel electric ®eld, and hence, the hot-carrier degradation, but not so large such that the maximum drive current is greatly reduced. This device is designed for room temperature operation. This means that by design, at room temperature, GF Rc 1. When this device is stressed at VGS VDS , the dominant damage mechanism is the injection of charge near the drain. Some of that charge gets trapped in the spacer oxide, either in the form of ®xed charge or as interface states. This results in an increase in Rc . However, since the GF Rc ratio is initially very small, and since the LDD doping is relatively large, this increase in resistance has little eect on the measured transconductance. Therefore, at room temperature, the VGS @ Ib max stress condition is the worst case. Now let us ex-
Fig. 20. Qualitative guide which relates the worst-case stress condition to the channel length and temperature [1].
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amine the situation at 78 K. For stress at the VGS @Ib max condition, the formation of interface states will likely be enhanced relative to stress at room temperature because of the increase in channel mobility with decreasing temperature. The damage is further enhanced since a given amount of Coulombic charge in the channel has a greater eect on the mobility at low temperatures. For the VGS VGD stress condition at 78 K, the injection of electrons into the drain region is also enhanced due to the increased channel mobility. Some of those electrons get trapped in the spacer oxide, either in the form of interface states or ®xed charge. At 78 K, however, the GF Rc ratio is no longer small since carrier freezeout has increased the Rc value dramatically. The eect of the charge trapping is to deplete a region of the LDD structure, resulting in a signi®cant increase in Rc . This eect is further magni®ed by the fact that a given amount of trapped charge will create a greater change in Rc at low temperatures where the eective LDD doping is less due to freezeout. As shown in Fig. 9, this is the dominant eect, and VGS VDS is the worst-case bias condition. For completeness, it should be noted that the trap eciency of the spacer oxide is greater at lower temperatures, where there is less thermal energy to detrap the weakly bound ®xed charge. For a longer channel length device, the intrinsic transconductance is even smaller, hence, it requires cooling the device to even lower temperatures to increase Rc suciently to see the cross-over in the worst-case stress condition. Now let us consider an L 1 lm device at room temperature. The above discussion of the eect of the two dierent stress conditions still holds. Now we will hold the temperature constant and decrease the channel length. As the channel length is decreased, let us assume that Rc remains constant. As the channel length is reduced, GF increases, and hence the GF Rc product increases. At some point, GF Rc becomes big enough such that changes in Rc associated with the VGS VDS stress condition become dominant and the worst-case bias condition crosses over from VGS @Ib max to VGS VDS . Hence, whenever GF Rc becomes suciently large, either by increasing Rc by decreasing the temperature, or by increasing GF by decreasing the channel length, a crossover in worst-case stress condition can occur. In real devices Rc does not remain constant as channel length is shrunk but rather decreases with decreasing channel length. The fact that a cross-over in worst-case bias condition is observed as channel length is shortened indicates that the decrease in Rc is slower than the increase in GF . This is not surprising when one considers the approach to determining the LDD doping level during device design as described in the ®rst paragraph of this section. If one only looks at the classical VGS @Ib max stress condition in determining the LDD doping level, then the possibility of damage at VGS VDS is being ignored. An improved methodology would
659
be to consider the damage associated with both stress conditions when determining the optimum LDD doping. In addition, alternative spacer materials, which have lower trapping eciencies, could help minimize the damage associated with charge trapping in the spacer region. Finally, it should be emphasized that in evaluating the worst-case stress condition for a given device, it is not sucient to look at one single stress voltage for each stress condition. As can be seen in Fig. 6, for example, that would lead to an erroneous conclusion of the worstcase stress condition to achieve a 10 year DC lifetime. Since the slope of the lifetime versus the inverse of the supply voltage are not the same, they may intersect as the supply voltage is decreased, resulting in a cross-over in worst-case stress condition to achieve a given lifetime. It is therefore necessary, at a minimum, to test at least four devices (two at each bias condition) so that the lifetime versus inverse supply voltage curves can be properly extrapolated.
5. Conclusions This paper investigated the underlying mechanisms that determine the cross-over in worst-case hot-carrier stress condition observed at room temperature in some deep submicron LDD NMOS devices and observed at cryogenic temperatures for devices with longer channel lengths. A series of experiments were performed on devices fabricated using ®ve dierent commercial processes that indicated the generality of the cross-over behavior. The role of stress temperature, measurement temperature and stress condition were experimentally addressed. The experiments indicate that the reason for the crossover in worst-case bias condition between maximum substrate current stress and maximum gate voltage stress at low temperature is not that the maximum gate voltage stress condition creates dramatically more damage to the device, but rather that the damage created produces larger shifts in the device performance. The temperature dependence of the mobility was measured, and an analysis showed that mobility changes alone could not explain the observed changes in the transconductance. A model was proposed that allowed for a change in the source±drain resistance with stress time. It was suggested that the origin of the time-dependent source±drain resistance was the injection of charge, either in the form of ®xed charge or as interface states, into the spacer oxide above the LDD region. This model was used to explain the qualitative dependence of the worst-case stress condition on channel length and temperature. Finally, it was suggested that the methodology used to design the LDD structure be modi®ed to account for these new observations.
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Acknowledgements The authors wish to acknowledge S. Brown and R. Robertson for help in packaging the devices, as well as D.C. Mayer for useful discussions. This work was supported by the US Air Force Space and Missile Center under contract no. F04701-93-C-0094. References [1] Wang-Ratkovic J, Lacoe RC, MacWilliams KP, Song M, Brown S, Yabiku G. New understanding of LDD CMOS hot-carrier degradation and device lifetime at cryogenic temperatures. Int Reliab Phys Proc 1997:312±9. [2] Li E, Rosenbaum E, Tao J, Yeap GC-F, Lin M-R, Fang P. Hot-carrier eects in nMOSFETS in 0.1 lm CMOS Technology. Int Reliab Phys Proc 1999:253±8.
[3] Heremans P, Van den Bosch G, Bellens R, Groeseneken G, Maes HE. Understanding of the temperature dependence of channel hot-carrier degradation in the range 77 K to 300 K, Tech Dig Int Electron Dev Meet 1989:67±9. [4] Song M, MacWilliams KP, Cable JS, Woo JCS. Bias and temperature dependence of hot-carrier lifetime from 77 K to 300 K. Tech Dig Int Electron Dev Meet 1992:707±10. [5] Watt JT. Modeling the performance of liquid-nitrogen cooled CMOS VLSI Tech Rep G725-3, Stanford Electronic Laboratory, Stanford, CA, May 1989. [6] Cheng B, Woo J. A temperature-dependent MOSFET inversion layer carrier mobility model for devices and circuit simulation. IEEE Trans Elec Dev 1997;44(2):343±5. [7] Chung SS, Lee J-S. A new approach to determine the drain and source series resistance of LDD MOSFET's. IEEE Trans Elec Dev 1993;40(9):1709±11. [8] Chung SS, Lin TS, Chen YG. An ecient semi-empirical model of the I±V characteristics for LDD MOSFET's. IEEE Trans Elec Dev 1989;36(9):1691±702.
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In¯uence of the lightly doped drain resistance on the worst-case hot-carrier stress condition for NMOS devices Everett E. King a, Ronald C. Lacoe a,*, Janet Wang-Ratkovic a,b a
The Aerospace Corporation, P.O. Box 92957-M2/244, Los Angeles, CA 90009-2957, USA b AMD, P.O. Box 3453, Sunnyvale, CA 94088-3453, USA Received 12 September 2000; received in revised form 29 December 2000
Abstract In this paper the underlying mechanisms that produce the cross-over in worst-case hot-carrier stress condition observed at room temperature in some deep submicron lightly doped drain (LDD) NMOS devices and at cryogenic temperatures for devices with longer channel lengths are investigated. Experiments were performed that demonstrate the generality of the cross-over. The role of stress temperature, measurement temperature and stress condition were experimentally addressed. The temperature dependence of the mobility was measured, and an analysis is presented that shows that mobility changes alone do not explain the observed changes in the transconductance. A model is proposed that allows for changes in the source±drain resistance with stress time. It is suggested that the origin of the timedependent increasing source±drain resistance is the injection of charge, either in the form of ®xed charge or as interface states, into the spacer oxide above the LDD region. This model is used to explain the qualitative dependence of the worst-case stress condition on channel length and temperature. Finally, it is suggested that the methodology used to design the LDD structure be modi®ed to account for these new observations. Ó 2001 Elsevier Science Ltd. All rights reserved.
1. Introduction Recently, Wang-Ratkovic et al. [1] presented a paper, which discussed the eect of cryogenic temperatures on the hot-carrier reliability of lightly doped drain (LDD) N-channel metal oxide semiconductor ®eld eect transistors (MOSFETs). Among the ®ndings they presented were that the worst-case hot-carrier stress condition was a function of both temperature and channel length. Two dierent stress conditions were investigated: (1) the stress condition associated with the classical room temperature substrate current model which predicts that the worst-case degradation occurs at a gate voltage corresponding to the maximum substrate current, VGS @Ib max or VGS 1=2 VDS , for which the device degradation is dominated by the formation of interface states; and (2) the maximum gate voltage stress, VGS VDS , that is
*
Corresponding author. Tel.: +1-310-336-0118; fax: +1-310336-5846. E-mail address: [email protected] (R.C. Lacoe).
normally associated with maximum gate current which results in electron injection into the oxide over the drain region of the device. Speci®cally, they found for the speci®c CMOS process tested that at cryogenic temperatures (78 and 125 K) the worst-case DC stress condition shifted from VGS @Ib max for channel lengths greater than 2 lm to VGS VDS for channel lengths less than 2 lm. For 2 lm channel length devices, they found a cross-over with stress time and drain voltage in the worst-case bias condition. Furthermore, the authors extended these results to produce a qualitative guide for predicting the worst-case stress condition over a broad range of temperatures and channel lengths. Among their conclusions was that even at room temperature, as devices scaled into the deep submicron regime, VGS VDS could become the worst-case hot-carrier stress condition. Li et al. [2] have recently observed that VGS VDS is the worst-case hot-carrier stress condition in NMOS devices with channel lengths below 0.25 lm. They attribute the cross-over in worst-case bias condition to a broadening of the substrate current versus gate voltage characteristics of devices as channel length is decreased.
0026-2714/01/$ - see front matter Ó 2001 Elsevier Science Ltd. All rights reserved. PII: S 0 0 2 6 - 2 7 1 4 ( 0 1 ) 0 0 0 0 7 - 5
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In this paper, we present new data on the room temperature hot-carrier degradation characteristics of a 0.25 lm LDD NMOS technology and ®nd that the worstcase bias condition corresponds to VGS VDS for large VDS , but as VDS decreases, the ratio of the degradation associated with a VGS VDS stress to a VGS @Ib max stress decreases. In addition, we present cryogenic hot-carrier stress data on two dierent CMOS processes which indicate that the above described cross-over in worst-case bias condition at cryogenic temperatures is a general property of LDD NMOS devices and is not speci®c to the particular CMOS process previously examined. Previous work [1,3,4] has shown that the measured damage for a device stressed at a given temperature and then evaluated at both room temperature and at cryogenic temperatures appears much larger at cryogenic temperatures. In this paper, new experiments are presented which illustrate the role of the stress condition on this eect. The second half of the paper attempts to explain the underlying physical mechanism responsible for these results. An experiment that compares the temperature dependence of the channel mobility of a virgin device to one stressed at room temperature demonstrates that the results cannot be explained by mobility degradation alone. A model is introduced that focuses on the role of the spacer oxide in explaining these results. In this model, the eect of charge injected into the spacer oxide above the LDD region is investigated. This model is used to qualitatively explain the dependence of the worst-case bias condition on temperature and channel length, as well as why the observed decrease in transconductance for a device stressed at room temperature is much larger at cryogenic temperatures. Finally, a recommendation is made to modify the methodology used to select the optimum LDD doping during the device design phase.
2. Experimental details The hot-carrier reliability of N-channel LDD MOSFETs fabricated using ®ve commercial processes from four vendors was investigated. Minimum channel lengths for the ®ve processes were 1.2 lm (process B), 1.0 lm (process D), 0.8 lm (process C), 0.5 lm (process E), and 0.25 lm (process A). It was found that the channel width had little, if any eect on the hot-carrier degradation. Thus, devices with dierent channel widths, but with the same channel length, were used interchangeably. The nominal thickness of the gate oxide in these processes is 21.5, 20, 15, 9.4, and 4 nm, respectively. The DC hot-carrier stressing and characterization were performed automatically using the HP 4155A semiconductor parametric analyzer in combination with
an HP BASIC test program. The program applied the user speci®ed stress voltages to the gate and drain of the device, stopping at prescribed intervals to characterize the device, and record the results. The deviceÕs linear threshold voltage (VT ) and maximum transconductance (Gm max ) were extracted from the current±voltage data and recorded. These measurements were made with the drain±source voltage set at 100 mV. All tests were conducted with the devices mounted in a Lakeshore MTD150 cryogenic dewar. The temperature at which the device was stressed and/or characterized was held constant using a Lakeshore Model 330 Autotuning temperature controller. The hot-carrier device lifetime was de®ned as the time required for a 10% degradation in the peak (maximum) linear transconductance. 3. Results In this section we present a series of new experimental results which address the role of channel length and temperature in determining the worst-case hot-carrier stress condition in LDD NMOS transistors. In Section 1, room temperature stress measurements on 0.25 lm devices will be presented which show that the worst-case stress condition is for VGS VDS . In Section 2, the role of the stress condition in two dierent LDD NMOS technologies is evaluated at cryogenic temperatures. The results are similar to those reported earlier [1], indicating that the cross-over eect with channel length at cryogenic temperatures is a general property of LDD NMOS devices. In Section 5, the dierent roles of stress temperature, stress condition, and characterization temperature are addressed. The results indicate that for devices stressed at VGS @Ib max , the decrease in hot-carrier lifetime between room temperature and 78 K is dominated by the dierence in actual damage to the device, while for devices stressed with VGS VDS , the large decrease in hot-carrier lifetime between room temperature and 78 K is associated with the observation that a small amount of damage at room temperature results in a large amount of apparent degradation at 78 K. 3.1. Room temperature stress measurements Figs. 1 and 2 show the Gm max degradation versus stress time at room temperature for short channel MOSFETs of 0.25 lm length fabricated using process A under stress conditions of VGS VDS and VGS @Ib max for VDS 4 and 3.3 V, respectively. For both the VDS 4 and 3.3 V stress conditions, contrary to the normal classical model where the VGS @Ib max stress condition is the worst case over the entire stress time domain, the VGS VDS is the worst-case stress condition for the ini-
E.E. King et al. / Microelectronics Reliability 41 (2001) 649±660
Fig. 1. Decrease in the normalized transconductance versus stress time at room temperature for L 0:25 lm devices for both VGS VDS and VGS @Ib max stress conditions with VDS 4 V.
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Fig. 3. Lifetime versus 1/VDS at room temperature for L 0:25 lm devices for both VGS VDS and VGS @Ib max stress conditions.
will depend on the lifetime criteria chosen. Extrapolating to determine the maximum DC voltage that will allow 10 years lifetime, one ®nds that for VGS VDS the maximum source±drain voltage is 2.13 V, while for the VGS @Ib max stress condition it is 2.25 V. The change in threshold voltage as a function of stress time for both stress conditions for a 0.25 lm MOSFET stressed at VDS 3:3 V is shown in Fig. 4. Unlike what was observed previously [1] and what was observed for the longer channel length MOSFETs in this study, there is a dramatic change in VT with hot-carrier stress. Both bias conditions degrade with similar temporal exponents and the degradation is slightly worse for the VGS @Ib max stress condition for long stress times.
Fig. 2. Decrease in the normalized transconductance versus stress time at room temperature for L 0:25 lm devices for both VGS VDS and VGS @Ib max stress conditions with VDS 3:3 V.
tial portion of the degradation curve. Since the slopes of the VGS VGD curves are less than that of the VGS @Ib max curves, the two curves eventually intersect. For both drain voltages, this intersection occurs near the lifetime criteria of a change in the normalized Gm max of 10%. Fig. 3 shows the lifetime (s) versus the inverse supply voltage (1/VDS ) at room temperature for the 0.25 lm MOSFETs. This plot includes additional stress data not shown in Figs. 1 and 2. This ®gure clearly shows that the worst-case stress condition for these transistors is the VGS VDS condition. However, since the degradation temporal exponents (Eq. (3)) are not the same, this result
Fig. 4. Decrease in the threshold voltage versus stress time at room temperature for L 0:25 lm devices for both VGS VDS and VGS @Ib max stress conditions with VDS 3:3 V.
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Fig. 5. Decrease in the normalized transconductance versus stress time at 120 K for L 1:2 lm devices for both VGS VDS and VGS @Ib max stress conditions with VDS 5 V.
Fig. 6. Lifetime versus 1/VDS at room temperature for L 1:2 lm devices for both VGS VDS and VGS @Ib max stress conditions.
3.2. Cryogenic temperature stress measurements To examine to what extent the cross-over in worstcase bias stress condition at cryogenic temperatures is general to LDD NMOS transistors, we investigated the hot-carrier stress properties of two dierent CMOS processes. In Fig. 5, the Gm max degradation versus stress time at 120 K is shown for MOSFETs with 1.2 lm channel lengths fabricated using process B (1.2 lm process) under stress conditions of VGS VDS and VGS @Ib max for VDS 5 V. The results indicate that VGS VDS is the worst-case stress condition, but that the two degradation curves have dierent temporal exponents, and will cross-over at suciently long times. The lifetime versus the inverse supply voltage at 120 K is shown in Fig. 6 for the 1.2 lm devices. Unlike for the 0.25 lm devices stressed at room temperature where the slope of the two s versus 1/VDS curves are nearly the same, the slopes for the 1.2 lm devices are suciently dierent at 125 K that the worst-case bias condition crosses over at low drain voltages. For 10 year lifetime, the worst-case stress condition is VGS @Ib max with the maximum operating voltage at 3.72 V, while for VGS VDS the maximum operating voltage is 4.01 V. These results are similar to what has been previously observed for 2 lm devices made with process D at 125 K [1]. For process C (0.8 lm process), the Gm max degradation versus stress time at 120 K for MOSFETs with 0.8 lm channel lengths under gate voltages of VGS VDS and VGS @Ib max for VDS 7 V is shown in Fig. 7. The results are qualitatively similar to those shown for the 1.2 lm device except that the lifetime is much shorter. It is interesting to note that the temporal exponents for both the process B and C transistors are nearly identical for the same stress condition. Fig. 8 shows the lifetime
Fig. 7. Decrease in the normalized transconductance versus stress time at 120 K for L 0:8 lm devices for both VGS VDS and VGS @Ib max stress conditions with VDS 7 V.
Fig. 8. Lifetime versus 1/VDS at room temperature for L 0:8 lm devices for both VGS VDS and VGS @Ib max stress conditions.
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versus the inverse supply voltage at 120 K for the 0.8 lm MOSFETs. For 10 year lifetime, the worst-case stress condition is VGS @Ib max with the maximum operating voltage is 3.46 V, while for VGS VDS the maximum operating voltage is 3.60 V. 3.3. Role of stress temperature versus measurement temperature Several dierent reports [1,3,4] have commented that a given amount of hot-carrier damage has a greater impact on device characteristics at lower temperatures than at higher temperatures. To gain additional insight into the cause of this eect we conducted a series of experiments in which the eects of stress temperature, measurement temperature and bias condition were isolated. A pair of L 1 lm LDD NMOS devices from process D (a 1 lm process) were stressed at room temperature at each of the two potential worst-case stress conditions. At speci®c stress intervals, the stress was interrupted and measurements of the transconductance were made at both room temperature and at 78 K. From these data, lifetimes for devices stressed at room temperature and characterized at room temperature could be determined, as well as the lifetime for devices stressed at room temperature but characterized at 78 K. Finally, a pair of nominally identical devices were stressed at 78 K and characterized at 78 K for the same source±drain voltage (VDS 5:5 V) used for the room temperature stress measurements. The results are shown in Fig. 9. The abscissa can be understood as follows: each position is for a given set of stress temperature/characterization temperature/stress conditions. For example, 292/292/IB means the device was stressed at 292 K, characterized at 292 K, and the stress condition was VGS @Ib max . Similarly, 292/78/IB means the device was stressed at 292 K, characterized at 78 K, and the stress condition was VGS @Ib max . Finally, 78/78/IB means the device was stressed at 78 K, characterized at 78 K, and the stress condition was VGS @Ib max . VG refers to the VGS VGD bias condition. The results provide an interesting perspective on the individual roles of the three variables. For the VGS @ Ib max stress condition, the eect of lowering the characterization temperature from 292 to 78 K results in less than an order of magnitude reduction in lifetime, while actually stressing the device and characterizing the device at 78 K results in nearly a two order of magnitude further decrease in lifetime. Hence, for the VGS @Ib max stress condition, the dominant factor in accounting for the decrease in lifetime between devices stressed at room temperature and devices stressed at 78 K is the damage done by the stress, not how that damage aects device characteristics. For the VGS VDS stress condition, the eect of lowering the characterization temperature from 292 to 78 K is dramatic ± approximately a ®ve order of
Fig. 9. Hot-carrier lifetime for an L 1 lm devices as a function of stress temperature, measurement temperature and bias condition, as described in the text.
magnitude decrease in lifetime. Actually stressing the device at 78 K results in less than an order of magnitude additional decrease in lifetime. Hence, for the VGS VDS stress condition, the dominant factor in the large decrease in lifetime when comparing a device stressed at 292 and 78 K is not that more damage is done by stressing the device at 78 K, but rather that the damage caused under this stress condition has a more dramatic eect on the measured transconductance at low temperatures. From this perspective, it now becomes clear that the reason there is a change in worst-case stress condition between devices stressed at room temperature and devices stressed at cryogenic temperatures is because the type of damage which occurs from a VGS VGD stress has a much more severe eect on device parameters at cryogenic temperatures than at room temperature and not that it produces more damage in the device.
4. Discussion In this section we will begin by addressing the role of the mobility in understanding the above-presented results. By measuring the maximum transconductance as a function of temperature for both a virgin device and a stressed device, we conclude that a decrease in channel mobility due to stress cannot alone account for the observed changes in the transconductance. We then present a model which examines the role of the series source± drain resistance and its eects on the measured transconductance. In this model, the source±drain resistance is allowed to change with stress. We then present experimental evidence that demonstrates and quanti®es the change in the source±drain resistance associated with carrier freezeout at cryogenic temperatures. We suggest that in addition to freezeout, the physical mechanism
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responsible for the change in source±drain resistance at ®xed temperature is the injection of electrons into the spacer oxide above the LDD region. Since this eect is enhanced by the VGS VGD stress condition, we can explain the results shown in Fig. 9 as well as the crossover in worst-case stress condition either as temperature is lowered for ®xed channel length, or as the channel length is reduced for ®xed temperature. Finally, the model is applied to explain the previously observed [1] change in temporal exponent for devices stressed at room temperature and characterized at room temperature, 125 and 78 K. 4.1. Role of channel mobility To gain further insight into the physical mechanisms responsible for determining the worst-case stress condition for a ®xed channel length transistor, we measured the temperature dependence of a 3 lm MOSFET fabricated using process D (1 lm process). Gm max versus temperature for the virgin device is shown in Fig. 10. The experimentally derived data is compared to that predicted by the standard MOSFET equation where the mobility is derived using the temperature-dependent model presented by Watt et al. [5]. In this model, the eective mobility is limited by three scattering mechanisms: phonon scattering, Coulombic (or charge) scattering, and surface roughness scattering, 1 1 1 1 : leff lph lC lsr
1
These three scattering mechanisms can be described by the following:
Fig. 10. Transconductance versus temperature for a virgin 3 lm device (process C). The solid line is the ®t to the mobility model described in the text. The dotted line represents the expected change in transconductance if the Coulombic term in the mobility model is increased to 20%.
a 106 1 1 Eeff l2 a 1 106 3 ; l3 Eeff
1 1 leff l1
1018 ot NB Nit N z
! 1
1012 Ninv
a2
2 where Eeff is the eective transverse electric ®eld, NB is the doping concentration, Nit and Not are the densities of interface states and ®xed trapped charge in the oxide, respectively, z is the width of the inversion layer, and Ninv is the density of carriers in the inversion layer. The values of the three temperature-dependent ls and as are process independent and have been empirically determined by Cheng and Woo [6]. As can be seen in Fig. 10, the experimental Gm max versus temperature data ®t the temperature dependence of the mobility model very well. Since hot-carrier-induced degradation is caused either by interface state buildup or charge trapping in the oxide, the only expected eect on the inversion layer mobility should be an increase in the Coulombic, or charge, scattering term. For example, the change in Gm max for a 20% increase in the Coulomb scattering term is also shown in Fig. 10. In this case, the predicted change in Gm max is a decrease of about 1.6% at room temperature (295 K) and 13% at 78 K. Post-stress Gm max versus temperature data in which the decreases in Gm max at room temperature and at 78 K are similar to those that were predicted in Fig. 10, are shown in Fig. 11. The best ®t to the temperaturedependent mobility model that can be obtained by allowing only the Coulomb scattering term to change is also shown in Fig. 11. It is observed that the ®t to these post-stress data is not as good as it is for the pre-stress
Fig. 11. Transconductance versus temperature for a device stressed at room temperature. The solid line is the best ®t of the mobility model allowing for changes only in Coulombic term.
E.E. King et al. / Microelectronics Reliability 41 (2001) 649±660
Gtot t
1 Rc GF t
655
1
:
6
It follows, using Eqs. (3) and (4), that the measured normalized transconductance is given by DGtot t Gtot 0 Gtot t Gtot 0 Gtot 0
Fig. 12. Equivalent circuit model for an intrinsic FET in series with the contact resistance associated with the source and drain structures.
data, suggesting that the hot-carrier-induced degradation is not totally due to a decrease in the channel mobility. 4.2. Source±drain resistance model 4.2.1. Constant source±drain resistance A simple model has been devised in order to gain insight into the mechanisms responsible for the observed device degradation as a function of temperature, channel length, and bias condition. In this model, the series resistance associated with the source and the drain regions are considered separate from the intrinsic ®eld eect transistor. This model is illustrated in Fig. 12, where the source and drain resistances are assumed equal with a value of Rc /2. Assuming a normal powerlaw degradation of the normalized transconductance with time, DGF t Atc1 b t=sc1 ; GF 0
b t=sc1 : 1 GF 0Rc 1 b t=sc1
7
Using Eq. (5), the parametric dependence of the normalized total transconductance versus time normalized to the lifetime for constant b 0:1 and c1 0:5 on the product GF (0)Rc is shown in Fig. 13. As can be seen in this ®gure, the eect of increasing Rc is to cause a parallel shift downward in the normalized transconductance versus time curve. Hence, the eect of increasing the value of the series resistance associated with the source±drain structures while assuming the intrinsic device degradation is unchanged is to increase the measured lifetime while leaving the eective temporal exponent unchanged. Physically, the above-described dependence can be understood as follows. While the eect of including a non-zero series resistance is to decrease the eective transconductance Gtot , the eect on DGtot is to decrease it even more strongly such that the normalized transconductance decreases. In fact, it can easily be shown that the lifetime sR c depends on GF (0)Rc as described by the equation sR c s 1 GF 0Rc c1 :
8
4.2.2. Time-dependent source±drain resistance We will now consider the case where the source±drain resistance is not constant, but changes as a function of
3
where GF (0) and GF (t) are the intrinsic FET transconductance before stress is applied and at time t after stress is initiated, respectively, c1 is the exponent, and s is the device lifetime de®ned by the condition DGF s b: GF 0
4
It follows that the temporal dependence of the FET transconductance can be expressed as GF t GF 01
b t=sc1 :
5
Experimentally, one does not measure the intrinsic FET transconductance, but rather a total conductance Gtot (t) consisting of the both the intrinsic FET transconductance and the conductance associated with the series resistance Rc :
Fig. 13. Normalized transconductance versus normalized time parameterized as a function of the GF Rc product for constant Rc .
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time. This could result from the injection of electrons into the spacer oxide above the source±drain LDD implant regions and/or the formation of interface states at the spacer oxide±LDD interface. Since the conductance is the inverse of the resistance, it follows that G
1 DG ) R G
DR : R
9
Assuming the source±drain resistance increases as a power law with time with lifetime sR and exponent c2 , the temporal dependence of the source±drain resistance can be described by Rc t Rc 01 b t=sR c2 :
10
De®ning C as the ratio of the resistance lifetime to the intrinsic FET lifetime, C s=sR ;
11
and
b Rc t Rc 0 1 c t=sc2 : C2
Fig. 14. Normalized transconductance versus normalized time parameterized as a function of the initial GF Rc product. In this parameterization, the source±drain resistance changes exponentially with exponent c2 0:25 and sR s:
12
Similar to the derivation of Eq. (5), it can be shown that DGtot t 1 Gtot 0
1
b t=sc1 1 GF 0Rc 0
1 GF 0Rc 01
b t=sc1
1 b : 1 c t=sc2 C2
13
To better understand the implications of Eq. (13), the normalized total transconductance versus normalized time for b 0:1, c1 0:5, c2 0:25 and sR s C 1 is plotted for dierent GF (0)Rc (0) products in Fig. 14. For Rc 0 0, the source±drain series resistance plays no role, and the results are identical to those observed in Fig. 13. At the other extreme, where GF 0Rc 0 10 and the source±drain series resistance dominates, the eective exponent for the degradation of the normalized total transconductance is that of the source±drain resistance degradation (0.25). For intermediary situations, the degradation does not follow a single exponent over the entire time domain. It can, however, be approximated by a single exponent between 0:001 6 t=s 6 1, where the value of the exponent is between 0.25 and 0.5, depending on the GF (0)Rc (0) product. The role of the value of the resistance lifetime parameter C is examined in Fig. 15. For b 0:1, GF 0Rc 0 1, c1 0:5 and c2 0:25, the eect of reducing C is to cause a parallel upward shift in the degradation curve such that the lifetime is reduced but the eective temporal exponent is unchanged. It is worth noting from Eq. (10) that the eect of changing the re-
Fig. 15. Normalized transconductance versus normalized time for ®xed c1 , c2 , GF Rc and dierent eective resistive lifetime constants.
sistance lifetime by a factor C relative to the intrinsic FET lifetime is equivalent to leaving the resistance lifetime unchanged but changing the lifetime criteria b by a factor of 1=C c2 : 4.3. Source±drain resistance measurements The series resistance of the LDD region was estimated for the 0.5 lm MOSFETs (process E) using the approach developed by Chung and Lee [7,8]. The mea-
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surements were made on a set of devices that had the same channel width of 11.2 lm, but channel lengths of 0.7, 1.4, 2.8, 5.6, and 11.2 lm. Gate voltage versus source±drain voltage measurements were made on this set of devices at a number of temperatures between 77 and 300 K. The source±drain series resistance was extracted for the data set obtained at each temperature following the referenced method. It was assumed that the portion of the drain±source series resistance corresponding to the leads, the source±drain contacts, and the source±drain regions behaves as a simple resistor with a constant temperature coecient. Thus, this resistance could be subtracted from the data set, leaving a resistance that should roughly correspond to the LDD resistance. The ®nal result is the resistance of the LDD region (Rc ) as a function of temperature, which is shown in Fig. 16. These results are consistent with the temperature dependence of carrier freezeout.
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Fig. 17. PISCES simulation of the decrease in the normalized transconductance versus charge deposited in spacer oxide for dierent LDD doping densities.
4.4. PISCES simulations PISCES simulations were performed to simulate the eect of and to better understand the device sensitivity to hot-carrier injected electrons that become trapped in the spacer oxide above the LDD region. In these simulations, the LDD region was 0.2 lm wide and 0.2 lm deep. Results for a 0.5 lm MOSFET are shown in Fig. 17. The decrease in Gm max is shown as a function of the amount of electron charge placed in a sheet at the surface of the LDD region, with the peak doping concentration in the LDD region as a parameter. First, it is seen that the presence of such a charge in the spacer oxide will signi®cantly degrade the transconductance. It is also shown that even a relatively small change in the peak doping concentration in the LDD region can greatly aect the amount of degradation that is observed for a given amount of ®xed charge. Clearly, the eective
Fig. 18. PISCES simulation of the change in the normalized threshold voltage.
decrease in peak doping concentration that is caused by carrier freezeout as temperature is lowered below 200 K will also signi®cantly increase the amount of degradation that occurs for this given ®xed charge in the spacer oxide. As shown in Fig. 18, the simulation also predicts changes in the threshold voltage. This result is consistent with the experimental results for an L 0:25 lm device (Fig. 4). For both the normalized transconductance and the threshold voltage, the largest eect is for the lowest doping density. This simply re¯ects that a given amount of injected charge will be a bigger percentage of the mirrored LDD charge for lower LDD doping density. 4.5. Application of the source±drain resistance model Fig. 16. Measured source±drain resistance Rc versus temperature.
In a previous study [1] the transconductance degradation versus stress time for an L 6 lm device stressed
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at 292 K at VGS @Ib max stress condition and measured at 292, 125, and 78 K was presented and is shown here in Fig. 19. We now illustrate that parameters can be chosen in the source±drain resistance model to provide a good match to the data. It was assumed that at room temperature the degradation is dominated by the intrinsic FET degradation, hence c1 0:76 was chosen and GRc 0:1 was assumed. The intrinsic FET lifetime was chosen to match the 292 K degradation curve and since the source±drain resistance changes have minimal eect at room temperature, C 1 was assumed. At 125 K, a choice of GRc 1 and c2 0:2 was made to match the experimentally determined exponent of 0.2. C was then chosen to shift the degradation curve up to intersect the data. At 78 K, c2 0:12, GRc 10 and C 0:001 yielded a good match to the data. As can be observed in Fig. 19 where the solid lines represent the predictions of the source±drain resistance model, the model is able to adequately describe the observed experimental results. While this is suggestive that the model is accurately describing the underlying physical mechanisms, it should be pointed out that the system is under constrained, and that there is more than one combination of c1 , c2 , GRc , and C which can be chosen to ®t the data. The parameters chosen to match the data indicate that the resistive lifetime is becoming very short at low temperatures. As discussed above, this re¯ects the fact that at low temperatures, due to carrier freezeout in the LDD region, a ®xed amount of trapped charge will represent a bigger percentage of the LDD charge, and hence, will have a bigger eect. Similarly, if one assumes charge is being trapped in the spacer oxide at a constant
Fig. 19. Change in normalized transconductance for an L 6 lm device stressed at 292 K at VGS @Ib max stress condition and measured at 292, 125, and 78 K [1]. The solid lines represent the prediction of the source±drain resistance model for the parameters speci®ed.
rate, the eect of carrier freezeout is that the LDD resistance increase will occur more rapidly and hence the resistance lifetime will be shorter. An additional mechanism that would also result in an upward shift of the damage curve is that the eect of interface charge on the channel mobility is more pronounced at low temperatures. 4.6. Worst-case stress condition dependence on L and T Within the above established framework of the role of the source±drain resistance and channel mobility on the hot-carrier degradation, it now becomes possible to explain the observed dependence of the worst-case stress condition on temperature and channel length as qualitatively described in Fig. 20. Let us begin by explaining the role of temperature by examining, for example, the eect of temperature on an L 1 lm device. At room temperature when the device is stressed at VGS @Ib max , the stress condition favors the formation of interface states near the drain and an associated decrease in the channel mobility. This results in a decrease in transconductance. An NMOS LDD device is ordinarily designed such that the source±drain resistance is large enough to reduce the maximum channel electric ®eld, and hence, the hot-carrier degradation, but not so large such that the maximum drive current is greatly reduced. This device is designed for room temperature operation. This means that by design, at room temperature, GF Rc 1. When this device is stressed at VGS VDS , the dominant damage mechanism is the injection of charge near the drain. Some of that charge gets trapped in the spacer oxide, either in the form of ®xed charge or as interface states. This results in an increase in Rc . However, since the GF Rc ratio is initially very small, and since the LDD doping is relatively large, this increase in resistance has little eect on the measured transconductance. Therefore, at room temperature, the VGS @ Ib max stress condition is the worst case. Now let us ex-
Fig. 20. Qualitative guide which relates the worst-case stress condition to the channel length and temperature [1].
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amine the situation at 78 K. For stress at the VGS @Ib max condition, the formation of interface states will likely be enhanced relative to stress at room temperature because of the increase in channel mobility with decreasing temperature. The damage is further enhanced since a given amount of Coulombic charge in the channel has a greater eect on the mobility at low temperatures. For the VGS VGD stress condition at 78 K, the injection of electrons into the drain region is also enhanced due to the increased channel mobility. Some of those electrons get trapped in the spacer oxide, either in the form of interface states or ®xed charge. At 78 K, however, the GF Rc ratio is no longer small since carrier freezeout has increased the Rc value dramatically. The eect of the charge trapping is to deplete a region of the LDD structure, resulting in a signi®cant increase in Rc . This eect is further magni®ed by the fact that a given amount of trapped charge will create a greater change in Rc at low temperatures where the eective LDD doping is less due to freezeout. As shown in Fig. 9, this is the dominant eect, and VGS VDS is the worst-case bias condition. For completeness, it should be noted that the trap eciency of the spacer oxide is greater at lower temperatures, where there is less thermal energy to detrap the weakly bound ®xed charge. For a longer channel length device, the intrinsic transconductance is even smaller, hence, it requires cooling the device to even lower temperatures to increase Rc suciently to see the cross-over in the worst-case stress condition. Now let us consider an L 1 lm device at room temperature. The above discussion of the eect of the two dierent stress conditions still holds. Now we will hold the temperature constant and decrease the channel length. As the channel length is decreased, let us assume that Rc remains constant. As the channel length is reduced, GF increases, and hence the GF Rc product increases. At some point, GF Rc becomes big enough such that changes in Rc associated with the VGS VDS stress condition become dominant and the worst-case bias condition crosses over from VGS @Ib max to VGS VDS . Hence, whenever GF Rc becomes suciently large, either by increasing Rc by decreasing the temperature, or by increasing GF by decreasing the channel length, a crossover in worst-case stress condition can occur. In real devices Rc does not remain constant as channel length is shrunk but rather decreases with decreasing channel length. The fact that a cross-over in worst-case bias condition is observed as channel length is shortened indicates that the decrease in Rc is slower than the increase in GF . This is not surprising when one considers the approach to determining the LDD doping level during device design as described in the ®rst paragraph of this section. If one only looks at the classical VGS @Ib max stress condition in determining the LDD doping level, then the possibility of damage at VGS VDS is being ignored. An improved methodology would
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be to consider the damage associated with both stress conditions when determining the optimum LDD doping. In addition, alternative spacer materials, which have lower trapping eciencies, could help minimize the damage associated with charge trapping in the spacer region. Finally, it should be emphasized that in evaluating the worst-case stress condition for a given device, it is not sucient to look at one single stress voltage for each stress condition. As can be seen in Fig. 6, for example, that would lead to an erroneous conclusion of the worstcase stress condition to achieve a 10 year DC lifetime. Since the slope of the lifetime versus the inverse of the supply voltage are not the same, they may intersect as the supply voltage is decreased, resulting in a cross-over in worst-case stress condition to achieve a given lifetime. It is therefore necessary, at a minimum, to test at least four devices (two at each bias condition) so that the lifetime versus inverse supply voltage curves can be properly extrapolated.
5. Conclusions This paper investigated the underlying mechanisms that determine the cross-over in worst-case hot-carrier stress condition observed at room temperature in some deep submicron LDD NMOS devices and observed at cryogenic temperatures for devices with longer channel lengths. A series of experiments were performed on devices fabricated using ®ve dierent commercial processes that indicated the generality of the cross-over behavior. The role of stress temperature, measurement temperature and stress condition were experimentally addressed. The experiments indicate that the reason for the crossover in worst-case bias condition between maximum substrate current stress and maximum gate voltage stress at low temperature is not that the maximum gate voltage stress condition creates dramatically more damage to the device, but rather that the damage created produces larger shifts in the device performance. The temperature dependence of the mobility was measured, and an analysis showed that mobility changes alone could not explain the observed changes in the transconductance. A model was proposed that allowed for a change in the source±drain resistance with stress time. It was suggested that the origin of the time-dependent source±drain resistance was the injection of charge, either in the form of ®xed charge or as interface states, into the spacer oxide above the LDD region. This model was used to explain the qualitative dependence of the worst-case stress condition on channel length and temperature. Finally, it was suggested that the methodology used to design the LDD structure be modi®ed to account for these new observations.
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Acknowledgements The authors wish to acknowledge S. Brown and R. Robertson for help in packaging the devices, as well as D.C. Mayer for useful discussions. This work was supported by the US Air Force Space and Missile Center under contract no. F04701-93-C-0094. References [1] Wang-Ratkovic J, Lacoe RC, MacWilliams KP, Song M, Brown S, Yabiku G. New understanding of LDD CMOS hot-carrier degradation and device lifetime at cryogenic temperatures. Int Reliab Phys Proc 1997:312±9. [2] Li E, Rosenbaum E, Tao J, Yeap GC-F, Lin M-R, Fang P. Hot-carrier eects in nMOSFETS in 0.1 lm CMOS Technology. Int Reliab Phys Proc 1999:253±8.
[3] Heremans P, Van den Bosch G, Bellens R, Groeseneken G, Maes HE. Understanding of the temperature dependence of channel hot-carrier degradation in the range 77 K to 300 K, Tech Dig Int Electron Dev Meet 1989:67±9. [4] Song M, MacWilliams KP, Cable JS, Woo JCS. Bias and temperature dependence of hot-carrier lifetime from 77 K to 300 K. Tech Dig Int Electron Dev Meet 1992:707±10. [5] Watt JT. Modeling the performance of liquid-nitrogen cooled CMOS VLSI Tech Rep G725-3, Stanford Electronic Laboratory, Stanford, CA, May 1989. [6] Cheng B, Woo J. A temperature-dependent MOSFET inversion layer carrier mobility model for devices and circuit simulation. IEEE Trans Elec Dev 1997;44(2):343±5. [7] Chung SS, Lee J-S. A new approach to determine the drain and source series resistance of LDD MOSFET's. IEEE Trans Elec Dev 1993;40(9):1709±11. [8] Chung SS, Lin TS, Chen YG. An ecient semi-empirical model of the I±V characteristics for LDD MOSFET's. IEEE Trans Elec Dev 1989;36(9):1691±702.