- Email: [email protected]
Outlook of MOS devices into next century
ELSEVIER
Microelectronic Engineering 48 (1999) 7-14
www.elsevier.nl/locate/mee
OUTLOOK OF MOS DEVICES INTO NEXT CENTURY Hiroshi Iwai Tokyo Institute of Technology 4259 Nagatsuta, Midori-ku, Yokohama, 226-8502, Japan Tel: +81-45-924-5471, Fax: 81-45-924-5487, E-mail:[email protected]
Silicon MOSFETs have achieved a great success as the primary component of LSls for 30 years by the downsizing. However, it is predicted that the downsizing will encounter certain limit in the early period of next century. This paper describes about the outlook of future of MOS transistors and LSIs in the next century in terms of its predicted limit and possibility of further evolution.
1.
INTRODUCTION
Since D. Kalmg and M. Atalla made the first SiMOSFET in 1960 [1], MOS devices started a great progress. In early 70's, MOSFETs were integrated in LSI and continued to make remarkable progress for almost 30 years. The first generation of LSIs, which appeared as products such as a 1Kbit DRAM and a 750 kHz MPU (Micro Processor Unit), has evolved up to 64Mbit DRAMs and 600 MHz MPUs, as shown in Table I. This evolution has seen the critical dimension (CD) decreases to 1/50, the number of memory bit increase by 256,000 times, and the MPU clock frequency increase by 800 times. Recent revolutionary progress in the information and communication fields, as represented by the Internet, and the popularization of intelligent mobile devices owes much to this remarkable development of LSI technologies. Such a tremendous growth of LSls illustrated in Table II has been achieved by the downsizing of components according to Moore's law [2], which says that CD decreases to 2/3, chip size increases to 3/2, and number of components in a chip quadruples every 3 years, or at every new generation. Regarding the future, this historical trend is expected to continue according to the SIA (Semicondu'etor Industry Association) National Technology Roadmap for Semiconductors [3] and its updated version - In-
temational Technology Roadmap[4] -, as shown in Table III, and continuous LSI growth is predicted until the 0.035 lain generation with gate length of 0.025 lxm in the year of 2014, though with a comment of no known solution to some of the requiremerits for the future generations. If the same trend is assumed up until 2059, the CD of LSI products will be less than the atomic distance in the silicon crystal. This would be the ultimate limit of conventional LSI. Before reaching this limit, however, we can expect certain other limitations to arise the reasons. In particular, the 0.1 lam generation expected to start in 2005 is already thought to be a critical stage because several limitations coincide. In spite of the expected limit in the downsizing, the downsizing of the MOSFETs has been accelerated year by year by year due to severe development competition among the chip suppliers which are aiming to release the next generation technology before the roadmap schedule, resulting in the revision for updating the roadmap as shown in Figs. 1 and 2. This paper describes on a personal view of the perspective of MOSFETs and MOS LSIs into the 21 st century, considering their possible limits in the early next century.
0167-9317/99/$ - see front matter © 1999 Elsevier Science B.V. All rights reserved. PII: S0167-9317(99)00328-7
H. lwai / Microelectronic Engineering 48 (1999) 7-14
Table I Evolution of LSI from 1970 m 1999 Year CD ratio DRAM bit 1970/72 10 Fm 1 1K 1998 0.18 i~m 1/50 256M CD: Critical Dimension Table II Historical trend of CD and number of DRAM bits Year 1970 1974 1977 1980 1983 CD (p,m) 10.0 6.0 4.0 3.0 2.0 Reduction -0.6 0.67 0.75 0.67 DRAM 1K 4K 16K 64K 256K
MPU clock 750 KHz 600 MHz
J ratio
256,000
1986 1.2 0.6 1M
Table III Future trend predicted by International Technol¢ 1999 Year 1997 0.18 Dense lines: Half pitch (tan) 0.25 0.72 Reduction 0.14 0.20 Isolated lines: MPU gate (Fm) 0.70 Reduction DRAM(~ samples/introduction 256M 1G 64M 256M DRAM ~production ramp MPU Clock frequency (MHz) 1250 On-chip, local, high performance 750 1200 On-chip, across the chip, high performance 375 600 On-chip, across the chip, cost performance 400 O, 0.3 . . . . . ~-. . . . . . . . . . . . . . . . . .
1989 0.8 0.67 4M
1989 0.5 0.63 16M
ratio 1 800
1995 0.35 0.70 64M
nap for Semiconductors u )dated 1998 2002 2005 2008 2011 0.13 0.10 0.07 0.05 0.72 0.77 0.7 0.71 0.10 0.07 0.05 0.035 0.71 0.70 0.71 0.70 4G 16G 64G 256G 1G 4G 16(3 64G 2100 1600 800
3500 2000 1100
6000 2500 1400
10000 3000 1800
1998 0.25 0.71 256M
2014 0.035 0.70 0.025 0.71 1T 256G 16903 3674 2303
%2-.
~
OA "O
"~ 0.07 0.05
~9 ~0 , 7. ,(,9~~I' , ~ " O SIA:
.
Semiconductor . Industry association
0.03 . . . . 1990
' ....
' .... 2000
-'~lt
~ _ "~
' ....
' -'~- 2010 "~
Year
Fig.l
Year
0.025~m
SIA Roadmap for isolated gate length
2. DOWNSIZING BY SCALING METHOD In digital circuit applications a MOSFET functions as a switch. Thus, complete cutoff of leakage current in the "off' state, and low resistance or high current drive in the "on" state are required. In addition small capacitances are required for the switch to rapidly turn on and off. When making the gate length small, even in the
5 25
0.5 0.4
Fig.2
0.37- 0.42V
SIA Roadmap for minimum supply voltage
"off" state, the space charge region near the drain the high potential region near the drain - touches the source in a deeper place where the gate bias cannot control the potential, resulting in a leakage electron current from source to drain via the space charge region as shown in Fig.3. This is the well-known short-channel effect of MOSFETs. The shortchannel effect is often measured as the threshold voltage reduction of MOSFETs when it is not severe.
H. lwai / Microelectronic Engineering 48 (1999) 7-14
shown in Fig. 4, resulting in the reduction of the space charge region by the same factor K and suppression of the short-channel effects.
0V 0v
Source l
T
Vdd (V)
[ Gate | [ l
1
Drain
,,all
Leakage Current - ~ ~ ~/~//'~//'J~///~/ / ~ ,
Space ChargeRegiorl~ "[J'-'~'--~U~'-"
-
Fig.3 Short-channel effect In order for a MOSFET to work as a component of an LSI, the capability of switching-off or the suppression of the short-channel effects is the first priority in the designing of the MOSFETs. In other words, the suppression of the short-channel effects limits the downsizing of MOSFETs. In the "on" state, reduction of the gate length is desirable because it decreases the channel reresistance of MOSFETs. However, when the channel resistance becomes as small as source and drain resistance, further improvement in the drain current or the MOSFET performance cannot be expected. Moreover, in the short-channel MOSFET design, the source and drain resistance often tends to even increase in order to suppress the short-channel effects. Thus, it is important to consider ways for reducing the total resistance of MOSFETs with keeping the suppression of the short-channel effects. The capacitances of MOSFETs usually decreases with the downsizing, but care should be taken when the fringing portion is dominant or when impurity concentration of the substrate is large in the shortchannel transistor design. Thus, for the MOSFET downsizing, the suppression of the short-channel effects with the improvement of the total resistance and capacitances are required. In other words, without the improvements of the MOSFET performance, the downsizing becomes almost meaningless even if the short-channel effect is completely suppressed. To suppress the short-channel effects and, thus, to secure good switching-off characteristics of MOSFETs, the scaling method was proposed by R. Dennard et al. [5], where the parameters of MOSFETs are shrunk or increased by the same factor K as
0 0
V
[X,Y,Z:I/K V:I/K Na'K ] IIK [DOCV/,/-~-~:IlK ,:l/K] I/K
I
I/K --
00
Fig.4
V IlK
Scaling method
So far, great success has been achieved with the scaling method in miniaturizing MOSFETs down to gate-lengths of 0.14 gm at the LSI product although the actual scaling of the parameters has been somewhat different from that originally proposed as the ideal scaling, as also shown in Fig. 5.
¢ ~ ~ ~ ~
1000 100
,o
10
-o
0.1 0.01 7O Fig.5
75
8O
88 9O H 20~ Year Trend of actual scaling for parameters
The major difference is the supply voltage reduction. The supply voltage was not reduced in the early phase of LSI generations in order to keep a compatibility with the supply voltage of conventional
10
H. lwai / Microelectronic Engineering 48 (1999) 7-14
systems and also in order to obtain higher operation speed under higher electric field. However, now, it is not easy to reduce the supply voltage because of difficulties in reducing the threshold voltage of the MOSFETs. Too small a threshold voltage leads to significantly large subthreshold leakage currem even at the gate voltage of 0 V.
.
LIMITS EXPECTED AT CRITICAL GENERATIONS
map shown in Table III to the year of 2059, CD of LSI products would become less than atomic distance in silicon crystal, and 64E (Exa:10 is) bit DRAM would be produced with a supply voltage of 2 mV as shown in Table IV. This would be the a) ultimate limit of LSI determined by the atomic distance. The gate electrode could be produced by atomic manipulation such by STM, but it is hardly believable that this works as a component of LSIs. Thus, anyway, the progress of the LSI by the component downsizing will encounter the hard limit by the middle of the next century at the longest.
If we could assume the same trend of the roadTable IV Simple extrapolation of the roadmap of Table HI to future and expected downsizing limiting factors
Mill L$ tox
2005 O.Igm (= lOOm) 0.07 ~m 1.5-2nm
2017 0.025 lain (= 25 nm) 0.018 ~m 0 . 4 - 0.5 nm
MinVd
0.9- 1.2 V
0.18 - 0.25 V
DRAM
16(3 bit (Gila : l0 s) e) Scaring parameter O Performance? g) Lithography? h) Interconnects?
256G bit
Year (Product) CD
Downsizmg Limiting factor
d)
Short-channel effects
2026 0.01 mn (= 10nm) 0.07 lxm O.15-0.2nm (= 1.5-2 A) 0.09 - O.12 V
2047 0.001 ~un (= Into) 0.0007 ~m 0.015 - 0.02 nm (=0. 15- 0.2 A) 0.009 - 0.012 V
1 6 T bit (Tera: 1012) b) Thermal noise? c) Uncertainty principle?
256P bit (Peta : I0Is)
2059 0.OOO25 tun (= 2.5 A) 0.00018 trot 0.004 - 0.005 ran (= 0.04 - 0.05 A) 0.0018 - 0.002 V (= 1.8- 2 mV) 64E bit ( E x a : l0 n) a) Atomic distance
MOSFET switch-off?
Before this limit, however, there are expected certain levels of limitation by several reasons as shown in the table. In the year of 2047, the device feature size would reach 1 nm, and it has been told that b) thermal noise and e) uncertainty principle would limit the transistor and LSI functions. In the year of 2017, we could reach the 25 nm generation paying a huge effort, hut the MOSFETs would not switch off due to the so-called d) short channel effects [6]. Especially, 0.1 I.tmgeneration is already thought to be a critical stage due to 5 downsizing limiting factors which relate each otlt~; e) scaling parameter, f) performance, g) lithography, h) imerconnects, and i) costs. Each factor is explained in the following sections.
4.
LIMITS BY SCALING PARAMETERS AND DEVICE PERFORMANCE
In order to realize sub-0.1 ~ n MOSFETs, significant modification of the scaling method is required because some of the parameters have already reached their scaling limitation in the 0.1 ~un generation as shown in Table V. In the 0.1 IJm generation, the gate oxide thickness has already reached the directtunneling leakage limit of 3 nm. The substrate impurity concentration (or the channel impurity concentration) has already reached 101Scm3. If the concentration is further increased, the sourcesuhstrate and drain-suhstrate junctions become highly doped pn junctions and act as tunnel diodes. Thus, the isolation of source and drains with substrate can-
11
H. lwai / Microelectronic Engineering 48 (1999) 7-14
not be maimained. The threshold voltage has already decreased to 0.2 - 0.4 V and further reduction causes significantly large subthreshold leakage current. Further reduction of the threshold voltage and thus, the further reduction of the supply voltage are difficult. Table V Scaling parameter
Lg xj tox Nsub Vd Vth
Scaling parameter limitation Value at 0.1pro generation 0.07 pan 20 - 40 am 1.5 - 2 nm 1E18/em3 0.9 - 1.2 V 0.2 - 0.4
7.0 6.0
-5.0 4.11
3.. I
limiting factor cost of lithography diffusion layer resistance direct-tunneling leakage direet-amneling leakage lower limit of Vth subthreshold leakage
01".| Fig.6
Lg tox
xj Nsub Vd
10LScm3
1
1.5V
1
40 nm 40 nm 3rim 10rim 10tSem-3 1.5 V
However, it was found that the deep sub-0.1 I~m MOSFETs - including the 40 nm Lg MOSFETs made without downsizing tox do not show any current drivability increase as shown in Fig. 7. By the experiment of 1.5 nm direct-tunneling oxide MOSFETs [8], it was confirmed that gate oxide should go beyond the direct-tunneling limit - 3 nm -, and the SIA roadmap was changed aggressively as shown in Fig. 8.
40 nm gate length n-MOSFET operation
1.$V,1.0V 3~V i ,~
:E~IO
,~)'SV,~L~.O v~ ( ~ _
Tox ,, 3 nm
live_ 1
i
i
|
~ ' "
0.01
. . . . . . . .
"
0.1
. . . . . . .
!
10
(a) gate oxide thickness
Table VI Sealing scheme used for 0.1 lain to 40 nm. Parameter values of 0.1 lam MOSFETs in 1993 was slightly different from those of Table IV. "-) 2/5 1 1/4
~
v~prl
As obvious from Table IV, if we would continue the simple scaling for future generations, tox, Vd, and Vth will soon become the unrealistically small values. Thus, in 1993, by using somewhat irregular sealing scheme as shown in Table VI - no further scaling of the tox, Nsub and Vd values, but instead, aggressive downsizing o f Lg and xj values -, successful operation of 40 nm gate length MOSFETs was without the short-channel effects was confirmed as shown in Fig. 6 [7].
0.1~m 0.1 pan 3rim 40 nm
8
1
~ 0.1
- "'r~___.
2., v 272"j,~ 2.1 v\l .
"0
.
i
0.01
~.0~;s'v"
|
0.01
. . . . . . .
.
/
.
.
.
.
.
.
.
.
.
.
"h L Vdd :'S V
1.6V |
.
. . . . . . . .
•
. . . . . . .
o.1 L~ (jan) 1 (b) Drain current
Fig.7 Correlation between the oxide thickness (a) and current derivability Co) plotted from pubfished data.
12
H. lwai / Microelectronic Engineering 48 (1999) 7-14
1 0
.
.
.
.
g
.
.
.
.
w
.
Lg [ iJm] 020xx
F t
.
.
.
|
1990
2000
.
.
.
m
.
.
.
.
~'e/~io~
18
-o 1o 007
4
"~.07
4
dido.14
tunneling ~
.
Year
2010
Fig.8 SIA Roadmap change for tox Progress of the LSI has been achieved by the downsizing of components, mainly because the ca-
paci.tance values decreases and thus switching time of the circuit decreases. This does not seem to be necessarily true when the CD decreases to 0. IBm and below. The problems related with the interconnects are explained in the interconnects section. Regarding the MOSFET downsizing, also performance improvement cannot be guaranteed in the generations of 0.1 Bm and below. Table VII shows the current status of the gate lengths for each level of front-end research and products. As described in the above, the minimum Lg achieved for transistor level (Lg = 0.04 Bin) does not give the highest.transistor performance (At this moment, it is given at Lg = 0.06 - 0.07 pro), and that the minimum Lg achieved for CMOS ring oscillator (Lg = 0.075 gtm) does not give the highest circuit performance (It is given at Lg = 0.1 lxm).
Table VH Gate lengths which give the highest performances Digital Logic
Tr Level
Min. Lg (Simulation) Mm. Lg (Experiment) Lg for max Id (Experiment) Lg for max gm (Experiment)
n-MOS: n-MOS: n-MOS: n-MOS: n-MOS: n-MOS:
0.025/am p-MOS: 0.025 Fm 0.04 Frn p-MOS: 0.05 lain 0.06 Fan ; 1.8mA/Fm @1.5 V 0.06 pan: 1120mS/ram @1.5 V 0.07 pan:>I 100mS/ram @I.5V 0.I0 pra: 1210mS/turn @2.5V
Circuit Min.L~ (Experiment) Level Lg for rain tpd (Experiment)
CMOS Rin80sc.: 0.075 pJn, 22ps @l.5V, 16ps @3.0V CMOS Rm~ Osc: 0.1 Hmi 8.0 ps @2.5V SOl CMOS Ring Osc: ~0.1 pro? (Leff=0.07pm);[email protected]
LSI Level
0.18pan : 550-600 MHz
MinLgforMPU(Products)
Thus, at this moment, the minimum Lg for MOSFET operation does not guarantee the maximum transistor, circuit or LSI performance. Large resistance caused by ultra-shallow S/D junction will harm the transistor and circuit performance, for example. For the logic devices, increase of the power consumption with increase in the clock ~equency is another major concern. The reduction of the supply voltage is the most effective method to reduce the power with the sacrifice of the clock speed. It should be noted that no circuit performance improvement has been realized below 0.1 Bm generation
even in the research level, even though deep sub-0.1 gm gate length MOSFETs were realized. This would lead to the downsizing limit in terms of the LSI performance. We hope this is solved by future development of downsizing technology.
5. DOWNSIZING LIMIT BY LITHOGRAPHY Lithography is the most fundamental process to realize the downsizing The progress of the lithography resolution has been achieved by the reduction of the wavelength used for the light for the exposure of the lithography. Now, 248 nm (or 0.248 pm) wave length light emitted from a KrF excimer laser is used
H. lwai I Microelectronic Engineering 48 (1999) 7-14
for 0.18 gm devices. It should be noted that the KrF is for the lithography which size is much shorter than the wavelength. In order to realize this, several kinds of resolution enhancement technique (RET) has been/are going to be developed. Furthermore, it is expected that 193 nm wavelength ArF light with combination of the RET will realize down to 0.13 lxm lithography in near future. So far, 0.13 ~tm generation would be handled by ArF stepper. One of the most serious problem, however, is that there is no light source commonly accepted in the industry for the next generation to ArF. There are several kinds of lithography techniques proposed, but none of them have been confirmed at this moment as the cost-effective candidate for further 0.1 ~tm and below. We hope this will be solved in near future. 6. LIMITS BY INTERFCONNECTS Interconnects are another big concern because the length of the interconnects and hence the number of interconnect layers continues to increase with generations. Thus, the number of the backend process steps increases, resulting in the significant production cost increase. Because the interconnect line becomes longer, narrower and denser for every generation, its resistance and capacitance increases dramatically. These RC delay and production cost for the interconnects would certainly work as a limiting factor to the downsizing in the regime of 0,1 tam and below. Of course, the introduction of the new techniques such as Cu-darnascene and low k interlayer material as shown would be very effective to extend the limit. However, the limitation of the interconnect multi-layer and downsizing will arrive in not far future. 8. OUTLOOK INTO THE NEXT CENTURY As described in the previous sections, the next century will featured by the i) end of downsizing, ii) end of gate oxide thinning, iii) end of the increase in integration iv) end of progress in clock frequency, in the middle range. However, it does not mean the end of the R & D in semiconductor industry and its progress. LSIs are now indispensable products for human society, similar as automobile, aircraft manufacturing or steel industries. Even though, the progress in the speed or size of the airplane saturate, there is always a huge market and R &D are indispensable to win the
13
competition. Furthermore, as the function of LSI evolves to higher level for handling more sophisticated operations, new appfication and market will be explosively increase, which would grow the semiconductor industry further. In the middle to short range, beginning of the next century will be an exciting period for the researchers, because now the research for new materials which would replace the gate oxide or poly Si gate electrode, etc. are really demanded and there is a high possibility that these new material somehow extend the downsizing limit of MOSFETs or LSIs. What would be a possibility of new device structures? In order to reduce the power consumption under considerably high speed operation in the mobile environment, higher drive current under lower bias is desirable. Single electron transistors does not seem to meet the requirement at this moment because of poor current drive or signal propagation capability. In the early period of the next century, telecommunication technology will make a huge progress. Under such an environment, high speed computations would be done by the base station and requirement to the high current drive would become less aggressive. What will be the future direction of technology development ? Will it leave the beaten path? Will there be any major breakthrough? Table VIII shows some of the major discovery and invention in electronics for done from the end of last century. Table VEIl Discovery and invention in electronics 1897 Discoveryof electrons by Thomson 1904 Invention of vacuum tube (Diode) by Fiemimg 1907 Invention of vacuum tube (Triode) by De Forest 1925 Invention of concept of MOSFET by Lilincf¢ld 1946 Realization of computer by Ec~ert and Mauchly 1947 Invention of bipolar Tr by Bardoca, Bratten, Shocklcy 1959,61 Invention of IC by Kilby and Noycc 1960 Realization of MOSFET by Kahng and Atalla 1970, 71 Fabrication of IkDRAM and 4bit MPU by Intel 1990's Interuct,mobile computation / telecommunication Considering such a tremendous progress in this century, it is impossible at all to predict the technology progress of next century. However, some personal view for the outlook of MOSFETs and LSIs in the next century is shown in Table XI, because this is the main objective of this paper. No one can make predictions about future breakthroughs, but it seems that an immediate revolution on the hardware side is unlikely.
14
H. lwai / Microelectronic Engineering 48 (1999) 7-14
Table IX Personal view: Outlook of the progress of MOSFET and LSI technologies
Hardware aspect
Software aspect
Economy Market aspect
21st century Early period Middle period Late period. $ Hardware performance limit?. ~, Downsizing limit?. 1' Suitable process and structure 1' Breakthrough for $ Interconnect problem? for new application or algorithm? process or device??? Lithography tool Problem? 1' Progress in new matedal introduction? 1" Software performance progress? I' Breakthrough in algorithm or amhitecture 1' New application like biological system?? more and more intelligent? more and more information &communication? more and more personal and mobile? ,I, Production cost increase J, Economy crisis in Asia. Russia, etc. 1' New market corresponding to the breakthrough $ Economy panic in the world.?? shown in the above?? 1' Increase in market size rapid growth in Chain, India etc.? new a p p l i ~ described in the above?
Rather than hardware, there is a better chance of a breakthrough, or at least of innovation, on the software side, such as new application, algorithm and system architecture side. 'Internet' would be one of the examples. It is one of the major forces to expedite the realiTation of the information community and thus to develop new application fields of LSIs. Popularization of the intelligent mobile devices is another example. In particular, it has been noted that today's computer architecture is much more inefficient than biological structures. Thus, there is room for revolutionary improvements in the efficiency of our computer structures at some point in the future. Once a breakthrough or innovation occurs on the software side, hardware will follow. New hardware demands imposed by new systems will become a strong motive force. In fact, the past development of digital LSIs has strongly depended on the conventional computer architectures. The discussion of the necessity of the downsizing in the roadmap has been made also on the premise of today's architecture. It is greatly expected that new algorithm and architecture of computer totally different from those of today wig promote the development of a completely new style of LSIs.
Even now, prototypes of future hardware device components might already be in existence simply waiting for suitable applications. Research on conventional path is still most important. It is likely that research on the introduction of many kinds of new materials - whether inorganic, organic, or even biological - to semiconductor devices will be the most productive; certainly this is an exciting area with potential for extending some limitation of LSIs. From the process research point of view, we look forward to new approaches that will dramatically reduce the production costs. Also, environmental issues must be considered of utmost importance in the development of any new techniques. REFERENCES 1. D. Kahng et al, IRE Solid-StateDev. Res. Conf., (1960). 2. G. E. Moore, IEDM Tech. Dig., p. 11, Docember, (1975) 3. Semico~_~_=torIndustry Association, 'The national technology rtmdm~ for semiconductors,' (1997) 4. Scmic,o~___wJ=orln~_t~ary Association, 'The international technologyroadmap for semiconductors:(1998) 5.1L H. Dennard et al., IEEE J. Solid-State Circuits, SC-9, p.256 (1974) 6. H. Iwai, IEEE J.Solid-State Circuits, vol.34, p.357 (1999) 7. M. Onoetal., IEDMTech. Dig.,p. 119,(1993). 8. H. S. Momos¢et al., IEDM Tech. p. 593 (1994)
Microelectronic Engineering 48 (1999) 7-14
www.elsevier.nl/locate/mee
OUTLOOK OF MOS DEVICES INTO NEXT CENTURY Hiroshi Iwai Tokyo Institute of Technology 4259 Nagatsuta, Midori-ku, Yokohama, 226-8502, Japan Tel: +81-45-924-5471, Fax: 81-45-924-5487, E-mail:[email protected]
Silicon MOSFETs have achieved a great success as the primary component of LSls for 30 years by the downsizing. However, it is predicted that the downsizing will encounter certain limit in the early period of next century. This paper describes about the outlook of future of MOS transistors and LSIs in the next century in terms of its predicted limit and possibility of further evolution.
1.
INTRODUCTION
Since D. Kalmg and M. Atalla made the first SiMOSFET in 1960 [1], MOS devices started a great progress. In early 70's, MOSFETs were integrated in LSI and continued to make remarkable progress for almost 30 years. The first generation of LSIs, which appeared as products such as a 1Kbit DRAM and a 750 kHz MPU (Micro Processor Unit), has evolved up to 64Mbit DRAMs and 600 MHz MPUs, as shown in Table I. This evolution has seen the critical dimension (CD) decreases to 1/50, the number of memory bit increase by 256,000 times, and the MPU clock frequency increase by 800 times. Recent revolutionary progress in the information and communication fields, as represented by the Internet, and the popularization of intelligent mobile devices owes much to this remarkable development of LSI technologies. Such a tremendous growth of LSls illustrated in Table II has been achieved by the downsizing of components according to Moore's law [2], which says that CD decreases to 2/3, chip size increases to 3/2, and number of components in a chip quadruples every 3 years, or at every new generation. Regarding the future, this historical trend is expected to continue according to the SIA (Semicondu'etor Industry Association) National Technology Roadmap for Semiconductors [3] and its updated version - In-
temational Technology Roadmap[4] -, as shown in Table III, and continuous LSI growth is predicted until the 0.035 lain generation with gate length of 0.025 lxm in the year of 2014, though with a comment of no known solution to some of the requiremerits for the future generations. If the same trend is assumed up until 2059, the CD of LSI products will be less than the atomic distance in the silicon crystal. This would be the ultimate limit of conventional LSI. Before reaching this limit, however, we can expect certain other limitations to arise the reasons. In particular, the 0.1 lam generation expected to start in 2005 is already thought to be a critical stage because several limitations coincide. In spite of the expected limit in the downsizing, the downsizing of the MOSFETs has been accelerated year by year by year due to severe development competition among the chip suppliers which are aiming to release the next generation technology before the roadmap schedule, resulting in the revision for updating the roadmap as shown in Figs. 1 and 2. This paper describes on a personal view of the perspective of MOSFETs and MOS LSIs into the 21 st century, considering their possible limits in the early next century.
0167-9317/99/$ - see front matter © 1999 Elsevier Science B.V. All rights reserved. PII: S0167-9317(99)00328-7
H. lwai / Microelectronic Engineering 48 (1999) 7-14
Table I Evolution of LSI from 1970 m 1999 Year CD ratio DRAM bit 1970/72 10 Fm 1 1K 1998 0.18 i~m 1/50 256M CD: Critical Dimension Table II Historical trend of CD and number of DRAM bits Year 1970 1974 1977 1980 1983 CD (p,m) 10.0 6.0 4.0 3.0 2.0 Reduction -0.6 0.67 0.75 0.67 DRAM 1K 4K 16K 64K 256K
MPU clock 750 KHz 600 MHz
J ratio
256,000
1986 1.2 0.6 1M
Table III Future trend predicted by International Technol¢ 1999 Year 1997 0.18 Dense lines: Half pitch (tan) 0.25 0.72 Reduction 0.14 0.20 Isolated lines: MPU gate (Fm) 0.70 Reduction DRAM(~ samples/introduction 256M 1G 64M 256M DRAM ~production ramp MPU Clock frequency (MHz) 1250 On-chip, local, high performance 750 1200 On-chip, across the chip, high performance 375 600 On-chip, across the chip, cost performance 400 O, 0.3 . . . . . ~-. . . . . . . . . . . . . . . . . .
1989 0.8 0.67 4M
1989 0.5 0.63 16M
ratio 1 800
1995 0.35 0.70 64M
nap for Semiconductors u )dated 1998 2002 2005 2008 2011 0.13 0.10 0.07 0.05 0.72 0.77 0.7 0.71 0.10 0.07 0.05 0.035 0.71 0.70 0.71 0.70 4G 16G 64G 256G 1G 4G 16(3 64G 2100 1600 800
3500 2000 1100
6000 2500 1400
10000 3000 1800
1998 0.25 0.71 256M
2014 0.035 0.70 0.025 0.71 1T 256G 16903 3674 2303
%2-.
~
OA "O
"~ 0.07 0.05
~9 ~0 , 7. ,(,9~~I' , ~ " O SIA:
.
Semiconductor . Industry association
0.03 . . . . 1990
' ....
' .... 2000
-'~lt
~ _ "~
' ....
' -'~- 2010 "~
Year
Fig.l
Year
0.025~m
SIA Roadmap for isolated gate length
2. DOWNSIZING BY SCALING METHOD In digital circuit applications a MOSFET functions as a switch. Thus, complete cutoff of leakage current in the "off' state, and low resistance or high current drive in the "on" state are required. In addition small capacitances are required for the switch to rapidly turn on and off. When making the gate length small, even in the
5 25
0.5 0.4
Fig.2
0.37- 0.42V
SIA Roadmap for minimum supply voltage
"off" state, the space charge region near the drain the high potential region near the drain - touches the source in a deeper place where the gate bias cannot control the potential, resulting in a leakage electron current from source to drain via the space charge region as shown in Fig.3. This is the well-known short-channel effect of MOSFETs. The shortchannel effect is often measured as the threshold voltage reduction of MOSFETs when it is not severe.
H. lwai / Microelectronic Engineering 48 (1999) 7-14
shown in Fig. 4, resulting in the reduction of the space charge region by the same factor K and suppression of the short-channel effects.
0V 0v
Source l
T
Vdd (V)
[ Gate | [ l
1
Drain
,,all
Leakage Current - ~ ~ ~/~//'~//'J~///~/ / ~ ,
Space ChargeRegiorl~ "[J'-'~'--~U~'-"
-
Fig.3 Short-channel effect In order for a MOSFET to work as a component of an LSI, the capability of switching-off or the suppression of the short-channel effects is the first priority in the designing of the MOSFETs. In other words, the suppression of the short-channel effects limits the downsizing of MOSFETs. In the "on" state, reduction of the gate length is desirable because it decreases the channel reresistance of MOSFETs. However, when the channel resistance becomes as small as source and drain resistance, further improvement in the drain current or the MOSFET performance cannot be expected. Moreover, in the short-channel MOSFET design, the source and drain resistance often tends to even increase in order to suppress the short-channel effects. Thus, it is important to consider ways for reducing the total resistance of MOSFETs with keeping the suppression of the short-channel effects. The capacitances of MOSFETs usually decreases with the downsizing, but care should be taken when the fringing portion is dominant or when impurity concentration of the substrate is large in the shortchannel transistor design. Thus, for the MOSFET downsizing, the suppression of the short-channel effects with the improvement of the total resistance and capacitances are required. In other words, without the improvements of the MOSFET performance, the downsizing becomes almost meaningless even if the short-channel effect is completely suppressed. To suppress the short-channel effects and, thus, to secure good switching-off characteristics of MOSFETs, the scaling method was proposed by R. Dennard et al. [5], where the parameters of MOSFETs are shrunk or increased by the same factor K as
0 0
V
[X,Y,Z:I/K V:I/K Na'K ] IIK [DOCV/,/-~-~:IlK ,:l/K] I/K
I
I/K --
00
Fig.4
V IlK
Scaling method
So far, great success has been achieved with the scaling method in miniaturizing MOSFETs down to gate-lengths of 0.14 gm at the LSI product although the actual scaling of the parameters has been somewhat different from that originally proposed as the ideal scaling, as also shown in Fig. 5.
¢ ~ ~ ~ ~
1000 100
,o
10
-o
0.1 0.01 7O Fig.5
75
8O
88 9O H 20~ Year Trend of actual scaling for parameters
The major difference is the supply voltage reduction. The supply voltage was not reduced in the early phase of LSI generations in order to keep a compatibility with the supply voltage of conventional
10
H. lwai / Microelectronic Engineering 48 (1999) 7-14
systems and also in order to obtain higher operation speed under higher electric field. However, now, it is not easy to reduce the supply voltage because of difficulties in reducing the threshold voltage of the MOSFETs. Too small a threshold voltage leads to significantly large subthreshold leakage currem even at the gate voltage of 0 V.
.
LIMITS EXPECTED AT CRITICAL GENERATIONS
map shown in Table III to the year of 2059, CD of LSI products would become less than atomic distance in silicon crystal, and 64E (Exa:10 is) bit DRAM would be produced with a supply voltage of 2 mV as shown in Table IV. This would be the a) ultimate limit of LSI determined by the atomic distance. The gate electrode could be produced by atomic manipulation such by STM, but it is hardly believable that this works as a component of LSIs. Thus, anyway, the progress of the LSI by the component downsizing will encounter the hard limit by the middle of the next century at the longest.
If we could assume the same trend of the roadTable IV Simple extrapolation of the roadmap of Table HI to future and expected downsizing limiting factors
Mill L$ tox
2005 O.Igm (= lOOm) 0.07 ~m 1.5-2nm
2017 0.025 lain (= 25 nm) 0.018 ~m 0 . 4 - 0.5 nm
MinVd
0.9- 1.2 V
0.18 - 0.25 V
DRAM
16(3 bit (Gila : l0 s) e) Scaring parameter O Performance? g) Lithography? h) Interconnects?
256G bit
Year (Product) CD
Downsizmg Limiting factor
d)
Short-channel effects
2026 0.01 mn (= 10nm) 0.07 lxm O.15-0.2nm (= 1.5-2 A) 0.09 - O.12 V
2047 0.001 ~un (= Into) 0.0007 ~m 0.015 - 0.02 nm (=0. 15- 0.2 A) 0.009 - 0.012 V
1 6 T bit (Tera: 1012) b) Thermal noise? c) Uncertainty principle?
256P bit (Peta : I0Is)
2059 0.OOO25 tun (= 2.5 A) 0.00018 trot 0.004 - 0.005 ran (= 0.04 - 0.05 A) 0.0018 - 0.002 V (= 1.8- 2 mV) 64E bit ( E x a : l0 n) a) Atomic distance
MOSFET switch-off?
Before this limit, however, there are expected certain levels of limitation by several reasons as shown in the table. In the year of 2047, the device feature size would reach 1 nm, and it has been told that b) thermal noise and e) uncertainty principle would limit the transistor and LSI functions. In the year of 2017, we could reach the 25 nm generation paying a huge effort, hut the MOSFETs would not switch off due to the so-called d) short channel effects [6]. Especially, 0.1 I.tmgeneration is already thought to be a critical stage due to 5 downsizing limiting factors which relate each otlt~; e) scaling parameter, f) performance, g) lithography, h) imerconnects, and i) costs. Each factor is explained in the following sections.
4.
LIMITS BY SCALING PARAMETERS AND DEVICE PERFORMANCE
In order to realize sub-0.1 ~ n MOSFETs, significant modification of the scaling method is required because some of the parameters have already reached their scaling limitation in the 0.1 ~un generation as shown in Table V. In the 0.1 IJm generation, the gate oxide thickness has already reached the directtunneling leakage limit of 3 nm. The substrate impurity concentration (or the channel impurity concentration) has already reached 101Scm3. If the concentration is further increased, the sourcesuhstrate and drain-suhstrate junctions become highly doped pn junctions and act as tunnel diodes. Thus, the isolation of source and drains with substrate can-
11
H. lwai / Microelectronic Engineering 48 (1999) 7-14
not be maimained. The threshold voltage has already decreased to 0.2 - 0.4 V and further reduction causes significantly large subthreshold leakage current. Further reduction of the threshold voltage and thus, the further reduction of the supply voltage are difficult. Table V Scaling parameter
Lg xj tox Nsub Vd Vth
Scaling parameter limitation Value at 0.1pro generation 0.07 pan 20 - 40 am 1.5 - 2 nm 1E18/em3 0.9 - 1.2 V 0.2 - 0.4
7.0 6.0
-5.0 4.11
3.. I
limiting factor cost of lithography diffusion layer resistance direct-tunneling leakage direet-amneling leakage lower limit of Vth subthreshold leakage
01".| Fig.6
Lg tox
xj Nsub Vd
10LScm3
1
1.5V
1
40 nm 40 nm 3rim 10rim 10tSem-3 1.5 V
However, it was found that the deep sub-0.1 I~m MOSFETs - including the 40 nm Lg MOSFETs made without downsizing tox do not show any current drivability increase as shown in Fig. 7. By the experiment of 1.5 nm direct-tunneling oxide MOSFETs [8], it was confirmed that gate oxide should go beyond the direct-tunneling limit - 3 nm -, and the SIA roadmap was changed aggressively as shown in Fig. 8.
40 nm gate length n-MOSFET operation
1.$V,1.0V 3~V i ,~
:E~IO
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Tox ,, 3 nm
live_ 1
i
i
|
~ ' "
0.01
. . . . . . . .
"
0.1
. . . . . . .
!
10
(a) gate oxide thickness
Table VI Sealing scheme used for 0.1 lain to 40 nm. Parameter values of 0.1 lam MOSFETs in 1993 was slightly different from those of Table IV. "-) 2/5 1 1/4
~
v~prl
As obvious from Table IV, if we would continue the simple scaling for future generations, tox, Vd, and Vth will soon become the unrealistically small values. Thus, in 1993, by using somewhat irregular sealing scheme as shown in Table VI - no further scaling of the tox, Nsub and Vd values, but instead, aggressive downsizing o f Lg and xj values -, successful operation of 40 nm gate length MOSFETs was without the short-channel effects was confirmed as shown in Fig. 6 [7].
0.1~m 0.1 pan 3rim 40 nm
8
1
~ 0.1
- "'r~___.
2., v 272"j,~ 2.1 v\l .
"0
.
i
0.01
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. . . . . . .
.
/
.
.
.
.
.
.
.
.
.
.
"h L Vdd :'S V
1.6V |
.
. . . . . . . .
•
. . . . . . .
o.1 L~ (jan) 1 (b) Drain current
Fig.7 Correlation between the oxide thickness (a) and current derivability Co) plotted from pubfished data.
12
H. lwai / Microelectronic Engineering 48 (1999) 7-14
1 0
.
.
.
.
g
.
.
.
.
w
.
Lg [ iJm] 020xx
F t
.
.
.
|
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2000
.
.
.
m
.
.
.
.
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18
-o 1o 007
4
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4
dido.14
tunneling ~
.
Year
2010
Fig.8 SIA Roadmap change for tox Progress of the LSI has been achieved by the downsizing of components, mainly because the ca-
paci.tance values decreases and thus switching time of the circuit decreases. This does not seem to be necessarily true when the CD decreases to 0. IBm and below. The problems related with the interconnects are explained in the interconnects section. Regarding the MOSFET downsizing, also performance improvement cannot be guaranteed in the generations of 0.1 Bm and below. Table VII shows the current status of the gate lengths for each level of front-end research and products. As described in the above, the minimum Lg achieved for transistor level (Lg = 0.04 Bin) does not give the highest.transistor performance (At this moment, it is given at Lg = 0.06 - 0.07 pro), and that the minimum Lg achieved for CMOS ring oscillator (Lg = 0.075 gtm) does not give the highest circuit performance (It is given at Lg = 0.1 lxm).
Table VH Gate lengths which give the highest performances Digital Logic
Tr Level
Min. Lg (Simulation) Mm. Lg (Experiment) Lg for max Id (Experiment) Lg for max gm (Experiment)
n-MOS: n-MOS: n-MOS: n-MOS: n-MOS: n-MOS:
0.025/am p-MOS: 0.025 Fm 0.04 Frn p-MOS: 0.05 lain 0.06 Fan ; 1.8mA/Fm @1.5 V 0.06 pan: 1120mS/ram @1.5 V 0.07 pan:>I 100mS/ram @I.5V 0.I0 pra: 1210mS/turn @2.5V
Circuit Min.L~ (Experiment) Level Lg for rain tpd (Experiment)
CMOS Rin80sc.: 0.075 pJn, 22ps @l.5V, 16ps @3.0V CMOS Rm~ Osc: 0.1 Hmi 8.0 ps @2.5V SOl CMOS Ring Osc: ~0.1 pro? (Leff=0.07pm);[email protected]
LSI Level
0.18pan : 550-600 MHz
MinLgforMPU(Products)
Thus, at this moment, the minimum Lg for MOSFET operation does not guarantee the maximum transistor, circuit or LSI performance. Large resistance caused by ultra-shallow S/D junction will harm the transistor and circuit performance, for example. For the logic devices, increase of the power consumption with increase in the clock ~equency is another major concern. The reduction of the supply voltage is the most effective method to reduce the power with the sacrifice of the clock speed. It should be noted that no circuit performance improvement has been realized below 0.1 Bm generation
even in the research level, even though deep sub-0.1 gm gate length MOSFETs were realized. This would lead to the downsizing limit in terms of the LSI performance. We hope this is solved by future development of downsizing technology.
5. DOWNSIZING LIMIT BY LITHOGRAPHY Lithography is the most fundamental process to realize the downsizing The progress of the lithography resolution has been achieved by the reduction of the wavelength used for the light for the exposure of the lithography. Now, 248 nm (or 0.248 pm) wave length light emitted from a KrF excimer laser is used
H. lwai I Microelectronic Engineering 48 (1999) 7-14
for 0.18 gm devices. It should be noted that the KrF is for the lithography which size is much shorter than the wavelength. In order to realize this, several kinds of resolution enhancement technique (RET) has been/are going to be developed. Furthermore, it is expected that 193 nm wavelength ArF light with combination of the RET will realize down to 0.13 lxm lithography in near future. So far, 0.13 ~tm generation would be handled by ArF stepper. One of the most serious problem, however, is that there is no light source commonly accepted in the industry for the next generation to ArF. There are several kinds of lithography techniques proposed, but none of them have been confirmed at this moment as the cost-effective candidate for further 0.1 ~tm and below. We hope this will be solved in near future. 6. LIMITS BY INTERFCONNECTS Interconnects are another big concern because the length of the interconnects and hence the number of interconnect layers continues to increase with generations. Thus, the number of the backend process steps increases, resulting in the significant production cost increase. Because the interconnect line becomes longer, narrower and denser for every generation, its resistance and capacitance increases dramatically. These RC delay and production cost for the interconnects would certainly work as a limiting factor to the downsizing in the regime of 0,1 tam and below. Of course, the introduction of the new techniques such as Cu-darnascene and low k interlayer material as shown would be very effective to extend the limit. However, the limitation of the interconnect multi-layer and downsizing will arrive in not far future. 8. OUTLOOK INTO THE NEXT CENTURY As described in the previous sections, the next century will featured by the i) end of downsizing, ii) end of gate oxide thinning, iii) end of the increase in integration iv) end of progress in clock frequency, in the middle range. However, it does not mean the end of the R & D in semiconductor industry and its progress. LSIs are now indispensable products for human society, similar as automobile, aircraft manufacturing or steel industries. Even though, the progress in the speed or size of the airplane saturate, there is always a huge market and R &D are indispensable to win the
13
competition. Furthermore, as the function of LSI evolves to higher level for handling more sophisticated operations, new appfication and market will be explosively increase, which would grow the semiconductor industry further. In the middle to short range, beginning of the next century will be an exciting period for the researchers, because now the research for new materials which would replace the gate oxide or poly Si gate electrode, etc. are really demanded and there is a high possibility that these new material somehow extend the downsizing limit of MOSFETs or LSIs. What would be a possibility of new device structures? In order to reduce the power consumption under considerably high speed operation in the mobile environment, higher drive current under lower bias is desirable. Single electron transistors does not seem to meet the requirement at this moment because of poor current drive or signal propagation capability. In the early period of the next century, telecommunication technology will make a huge progress. Under such an environment, high speed computations would be done by the base station and requirement to the high current drive would become less aggressive. What will be the future direction of technology development ? Will it leave the beaten path? Will there be any major breakthrough? Table VIII shows some of the major discovery and invention in electronics for done from the end of last century. Table VEIl Discovery and invention in electronics 1897 Discoveryof electrons by Thomson 1904 Invention of vacuum tube (Diode) by Fiemimg 1907 Invention of vacuum tube (Triode) by De Forest 1925 Invention of concept of MOSFET by Lilincf¢ld 1946 Realization of computer by Ec~ert and Mauchly 1947 Invention of bipolar Tr by Bardoca, Bratten, Shocklcy 1959,61 Invention of IC by Kilby and Noycc 1960 Realization of MOSFET by Kahng and Atalla 1970, 71 Fabrication of IkDRAM and 4bit MPU by Intel 1990's Interuct,mobile computation / telecommunication Considering such a tremendous progress in this century, it is impossible at all to predict the technology progress of next century. However, some personal view for the outlook of MOSFETs and LSIs in the next century is shown in Table XI, because this is the main objective of this paper. No one can make predictions about future breakthroughs, but it seems that an immediate revolution on the hardware side is unlikely.
14
H. lwai / Microelectronic Engineering 48 (1999) 7-14
Table IX Personal view: Outlook of the progress of MOSFET and LSI technologies
Hardware aspect
Software aspect
Economy Market aspect
21st century Early period Middle period Late period. $ Hardware performance limit?. ~, Downsizing limit?. 1' Suitable process and structure 1' Breakthrough for $ Interconnect problem? for new application or algorithm? process or device??? Lithography tool Problem? 1' Progress in new matedal introduction? 1" Software performance progress? I' Breakthrough in algorithm or amhitecture 1' New application like biological system?? more and more intelligent? more and more information &communication? more and more personal and mobile? ,I, Production cost increase J, Economy crisis in Asia. Russia, etc. 1' New market corresponding to the breakthrough $ Economy panic in the world.?? shown in the above?? 1' Increase in market size rapid growth in Chain, India etc.? new a p p l i ~ described in the above?
Rather than hardware, there is a better chance of a breakthrough, or at least of innovation, on the software side, such as new application, algorithm and system architecture side. 'Internet' would be one of the examples. It is one of the major forces to expedite the realiTation of the information community and thus to develop new application fields of LSIs. Popularization of the intelligent mobile devices is another example. In particular, it has been noted that today's computer architecture is much more inefficient than biological structures. Thus, there is room for revolutionary improvements in the efficiency of our computer structures at some point in the future. Once a breakthrough or innovation occurs on the software side, hardware will follow. New hardware demands imposed by new systems will become a strong motive force. In fact, the past development of digital LSIs has strongly depended on the conventional computer architectures. The discussion of the necessity of the downsizing in the roadmap has been made also on the premise of today's architecture. It is greatly expected that new algorithm and architecture of computer totally different from those of today wig promote the development of a completely new style of LSIs.
Even now, prototypes of future hardware device components might already be in existence simply waiting for suitable applications. Research on conventional path is still most important. It is likely that research on the introduction of many kinds of new materials - whether inorganic, organic, or even biological - to semiconductor devices will be the most productive; certainly this is an exciting area with potential for extending some limitation of LSIs. From the process research point of view, we look forward to new approaches that will dramatically reduce the production costs. Also, environmental issues must be considered of utmost importance in the development of any new techniques. REFERENCES 1. D. Kahng et al, IRE Solid-StateDev. Res. Conf., (1960). 2. G. E. Moore, IEDM Tech. Dig., p. 11, Docember, (1975) 3. Semico~_~_=torIndustry Association, 'The national technology rtmdm~ for semiconductors,' (1997) 4. Scmic,o~___wJ=orln~_t~ary Association, 'The international technologyroadmap for semiconductors:(1998) 5.1L H. Dennard et al., IEEE J. Solid-State Circuits, SC-9, p.256 (1974) 6. H. Iwai, IEEE J.Solid-State Circuits, vol.34, p.357 (1999) 7. M. Onoetal., IEDMTech. Dig.,p. 119,(1993). 8. H. S. Momos¢et al., IEDM Tech. p. 593 (1994)