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Modes of failure of MOS devices
Microelectronics and Reliability
Pergamon Press 1971. Vol. 10, pp. 325-338.
Printed in Great Britain
MODES OF FAILURE OF MOS DEVICES W. ECCLESTON* a n d M. PEPPER
The Plessey Company Limited, Allen Clark Research Centre, Caswell, Towcester, Northants., England A b s t r a c t - - A review is presented of the physical basis of loss of yield and failure of integrated
circuits containing MOS devices. The causes of variations in both threshold voltage and other parameters are described. The effects of oxide and silicon defects on chip yield and reliability are discussed. Also included is a diagnostic table summarizing the means of distinguishing between the various modes of failure. All the physical effects are described with reference to p-channel aluminium gate devices. Extension of the results to other forms of MOS device should in most cases be obvious, as should the recognition of the phenomena on capacitance-voltage curves.
INTRODUCTION
THE fabrication of single-layer aluminium gate M O S integrated circuits requires four photoengraving operations: one diffusion, three oxidations and a metallization. W h e n compared with bipolar technology this represents a considerable reduction in process complexity and thus implies a higher yield and lower cost. By its nature, however, M O S has modes of failure due to phenomena which are often considered to be of secondary importance in bipolar technology. Most of the phenomena are associated with the properties of thermally oxidized silicon. A vast amount of information is available on the properties of the silicon dioxide-silicon system. Relating these properties to the electrical behaviour of M O S devices is not always easy. T h e purpose of this review is to summarize all the phenomena both in the literature and found by the authors, which are responsible for the failure of M O S devices. T h e physical concepts are presented with a reference to more comprehensive treatments elsewhere in the literature. W h e r e it has been necessary to discuss concepts not explicitly treated in the literature, then a more complete discussion is presented. T h e modes of failure are all described, for convenience, with reference to p-channel aluminium gate devices.
Extension of the concepts to n-channel or autoregistered devices should in most cases be obvious. 1. FIELD-DEPENDENT T H R E S H O L D
VOLTAGE 1.1 Mobile ions T h e threshold voltage of an M O S device is that voltage required to produce an inversion layer in the silicon and thereby a conducting surface layer between the source and rain. This voltage is determined by the amount of charge associated with the oxide and interface, as well as by the resistivity of the silicon and the work function difference between the metal and the underlying silicon. T h e amount of charge associated with the oxide can be affected by the presence of impurities such as alkali ions. These will have a positive charge and will therefore tend to increase the threshold voltage of p-channel devices. T h e effect of ions moving in the oxides of M O S structures can best be understood from a simplified model depicted in Fig. 1. A strip of charge, Q, is considered to exist somewhere in the oxide parallel to, and distance x from, the metal electrode. T h e total oxide thickness is x 0. By application of Gauss's Law to this situation it is readily shown that X
Q s c = Q xo
(1)
and
*Now at Dept. of Electronic and Electrical Engineering, University of Liverpool, U.K. 325
QM = Q (*0--x) X0
(2)
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W. E C C L E S T O N i
and M. P E P P E R
(c) If the surface of the oxide can be converted to a form which will render ions immobile, I I on then ions will, upon entering this region, be rendered harmless, as x in equation (l) will X be small. This is the basis of "phosphorus o (v~) stabilization. ''(l-a) T h e surface of an oxide is Xo stabilized by subjecting it to a phosphorus Oxide diffusion. During the deposition ions will migrate to the surface and become "locked" _~ _ _ in position because of the presence of deep trapping sites. This also applies to ions which can enter from the ambient. In this condition FIG. 1. The effect of charge within a dielectric on the (from equation (1)) the ions have a minimal semiconductor surface charge for an MOS structure. effect on the value and stability of the threshFrom Gauss' Law hold voltage. T h e relaxation times for ionic instability can be of the order of a few milliseconds at 200°C. (4, a) T h e direction of threshold voltage shift for a given polarity of bias is always the same whether the ions are where g = dielectric constant of oxide, K0 = dielectric positive or negative (less negative threshold constant of free space, also Qs~+QM=Q, voltage for negative stress on the gate). T h e hence equations (1) and (2) are easily proven for VM = 0. application of negative voltage to a gate electrode causes movement of mobile positive oxide charge to the gate. From equation (1) this will produce a less negative threshold where Qsc and QM are the charges induced in the voltage on p-channel devices, as the surface semiconductor and metal respectively by the will be less accumulated and nearer to inverpresence of the charged strip Q. sion. If the ions were negative, with negative As the strip of charge moves nearer to the metal bias applied to the gate electrode, they will the charge induced in the semiconductor becomes move towards the semiconductor inducing less, and when the strip of charge is coincident positive charge in the substrate (or removing with the metal the induced charge in the substrate negative charge). This will cause the semiconis zero. ductor surface to be less accumulated and will It is known that mobile charge tends to migrate reduce the voltage required to produce inverduring processing to the surface of the oxide. This sion. Hence both positive and negative ions has three important implications: will, for a given bias on the gate, cause the (a) Under negative biassing at temperature the same direction of change of threshold voltage. shift in the threshold voltage is less than one T h e field dependence of relaxation times can c4, 5) would expect from a uniform distribution of ions, but larger shifts will be seen for positive be of the form: temperature bias stressing. It is not always possible to do the positive biassing as it is now common to include gate protection In the absence of an electric field the migration diodes, to protect the gate against a large of ions is governed by the diffusion equation: voltage build-up. These diodes will under 02N ON positive gate conditions become forward D Ox2 Ot biassed. (b) Etching a thin layer of oxide after growth where N is the ionic concentration. can often remove a high percentage of the T h e diffusivity D can be represented by: contaminant. This can, unfortunately, lead to D = Doe-WqlkT another failure mode described in Section 3. • Metal
[ V~ I
f
=0
MODES
OF FAILURE
OF MOS
DEVICES
327
I I
I
--,~---u
P
Distance
FIG. 2. T h e superposition of a field on a potential well.
where D Ois constant and W is the activation energy for diffusion. In the presence of an applied electric field (E), the potential barrier to ionic motion becomes modified, as shown in Fig. 2. If E ~ k__T the q~ diffusion equation becomes:
aN
02N
ON
Ot -- D -~xxz--[~E(x)] O--x
where ~t is the ionic mobility. The solution of this equation is complex as the field across the oxide is not constant but is modified by the space charge of the ions themselves and changes of structure in the oxide. (e) For these reasons analysis of ionic migration in MOS structures is not straightforward. Activation energies can be dependent on the details of oxide preparation. 1.2 Polarization of phosphorus The use of phosphorus as a stabilizing agent is well known and documented. (x-3) It is unfortunate, however, that it can give rise to a qualitatively similar form of instability to that of mobile ions.(7, 8) This instability of threshold voltage is caused by polarization of the phosphorus doped oxide layers. The application of field and temperature to the device causes strips of charge to appear at the metal-glaze interface and at the glaze-oxide interface. From Fig. 1 and equation (1) it can be seen that although the two strips of charge should be equal and opposite in amount, they will have different effects on the surface potential of the
silicon. It is therefore important to make the glass layer a small fraction of the total oxide thickness, consistent with effective gettering of impurity ions. The amount of phosphorus included in the glass is also important. The direction of threshold voltage shifts is the same as for ionic instability, for a given polarity of stressing voltage. It is, however, distinguishable from positive mobile ions by the ability of this polarization to move the threshhold voltage through zero. This is not possible with mobile ions as they are usually positively charged, as is the net charge associated with surface states and fixed oxide charge. 1.3 Slow trapping A widely experienced mode of behaviour seen on MOS devices is the threshold voltage becoming more negative on application of negative bias to the gate. (9-11) This is the opposite type of shift to that caused by mobile ions and phosphorus polarization. It is usually caused by changes in the occupancy of traps a few angstroms from the oxide-silicon interface. Carriers from the silicon surface can enter the traps by tunnelling. These have long relaxation times and will induce charge entirely in the silicon surface, altering the threshhold voltage of the device. This phenomenon has been known since early work on the free surfaces of semiconductors, (1°) and is particularly severe between deposited oxides and semiconductor surfaces. In this case the instability has relaxation times of seconds and can be seen as hysteresis on slowly swept device characteristics or capacitancevoltage curves. These traps are differentiated from
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W. E C C L E S T O N and M. PEPPER
faster interface states by their response time. (In the case of fast surface states relaxation times of 10.8 sec 112~ are not unusual.) It is, of course, possible for the two forms of instability to be present simultaneously and cases of fast ionic instability followed by a slow recovery due to slow trapping have been reported. (9~ Slow trapping is increased by subjecting the device to ionizing radiation; for example, 1 keV electron bombardment will create such traps. Fortunately much of this instability can be removed by low temperature (<600°C) anneals in the presence of moisture or hydrogen, or by careful choice of aluminium sintering conditions, n3, 14~ A not dissimilar effect is obtained with oxidenitride sandwich gate dielectrics. The different conductivity of the two dielectrics results in a build-up of charge at the interface between them and this will cause threshold voltage shifts. This is the mode of action of the MNOS, a variable threshold device. To obtain maximum switching speed in this device, the current through the oxide layer should be controlled by tunnelling from the silicon, a5-17) This necessitates a very thin oxide layer and the behaviour of this type of device is quantitatively very similar to that expected from slow trapping.
The temperature dependence of the effect is not known, nor is the cause. 2. SPATIAL VARIATION IN THRESHOLD VOLTAGES
2.1 Mobile ions and other field dependent effects Variations in the concentrations of mobile ions, slow traps or phosphorus polarization can cause threshold voltage variations across a slice. These can be quantified by application of field and temperature to the MOS gates. In the case of mobile ions the spread of threshold voltage is reduced after negative biassing at temperature. The spread of threshold voltages is likely to become worse if the cause of the variations is phosphorus polarization. The instability caused by slow traps is very dependent on the average density of the traps and their energy level. It is not possible to generalize about the effect of these on spatial variations of threshold voltage.
2.2 Effect of resistivity variations Crystals of silicon grown by the Czochralski technique show a radial distribution of resistivity. This affects the amount of charge which needs to be applied to the gate of the device to pass from the normally accumulated condition (on n-type substrates), to inversion. For p-channel devices 1.4 Mobility instability the convention widely used for defining inversion It has been demonstrated by Murphy et al., (18~ is that surface potential at which the surface is as using surface Hall effect measurements, that appli- p type as the bulk is n type. This definition can be cation of a field to the gate of a device can cause a used to calculate the effect of resistivity variations change in the carrier surface mobility with time. on threshold voltage. The surface potential is This is the true surface mobility defined as assumed to be 2~B where ~B is the potential difference between real and intrinsic fermi levels. da It has been found by the authors that these caldQsc culated variations are often larger than those found where a is the surface conductance. This quantity in practice. Furthermore, experimental variations is different from the field effect mobility which is do not have the spatial variations expected from resistivity changes across a slice. An explanation of defined as d~ this may be obtained from the work of Murphy ~tQg" et al., (lsl where large changes of surface mobility The latter includes the effect of trapping in surface are measured at threshold. This could indicate states and is not a true mobility, but a method of that the surface conductance is limited more by combining all the factors reducing the surface con- mobility than carrier concentration and thus the ductance into one term having dimensions of effects of bulk resistivity variations are rendered mobility. Since Murphy's technique measures true negligible. surface mobility the effect must be different from that of slow trapping, although it is in the same 2.3 Variations in fast surface state density After oxidation there are wide variations in direction for a given sign of voltage stress and field.
M O D E S OF F A I L U R E OF MOS D E V I C E S surface state density across the silicon surface. A significant reduction is obtained by optimizing the aluminium sintering conditions, or by one of several other low temperature heat treatments. (m I f these surface states are not completely removed, then because of the initial spread in their density one might expect variation in device parameters. These surface states may be important not only from the point of view of threshold voltage, but also in determining the value of
( dI, I g~ = ~ / v a where Ia is the drain current and Vg is the gate voltage. The simple MOS equation below pinchoff:
~a= ~Co![(v~-v~)v~-?] gives dla b - ~Co- va dVg
(3)
where C O = the capacitance per unit area of the gate b = the aspect ratio of the channel defined as a
the ratio of channel width to channel length Va = the applied source drain voltage and = ~Fe is the field effect mobility defined
329
temperature heat treatments on mid-gap states has not been studied in detail. The indications are that this state is less affected by the aluminium sintering conditions and hence may have a large effect on threshold voltage variations. Because of its energy, however, this state is unlikely to have a large effect o n gin.
The effect of the conduction band surface state on threshold voltage is not easy to ascertain. Our knowledge of the surface states at the silicon interface only extends to being able to assign a density and energy to a state. No obvious method exists for ascertaining whether the states are donor-like or acceptor-like. For inversion of n-type silicon a donor state at the conduction band edge will be positively charged (as it will be unoccupied by electrons) and could have a pronounced effect on threshold voltage. If it is an acceptor, however, it will be neutral and will remain so in depletion and inversion with little effect on threshold voltage. The normal convention for defining surface state density and oxide charge assumes that the conduction band state is an acceptor and the valence band state is a donor. It should be noted that, at present, this is no more than a convention. Irrespective of its type, the conduction band state will have little effect on gm for a given value of
(v~-v~,). 3. GATE OXIDE LEAKAGE
Gate leakage currents can be caused by gate protection diffusions with weak diode characteristics or by imperfections in the gate or other oxides. d~ earlier as dQg" The case of weak junction characteristics is described in Section 8. Dielectric imperfections can We can rewrite the expression for field effect be caused by a large number of factors. One of the mobility in the form: most easily recognized is that due to ineffective photoresist masking at contacts photo-engraving. d6 d6 Imperfect photo-engraving masks may contain ~FE -- dQg -- d(Qss+Osc)" pinholes or spots. Depending on the type of I f Qss is the sum of fixed charge and surface photoresist used these may cause small regions of state charge then dQss is the change of charge in the gate oxide not to be protected, which are etched surface states. For a state near the valence band away during the normal etching of contacts. The d Q s s will be finite and hence ~ B will be reduced. contacts are, in the case of aluminium gate devices, It is known that there exist states in mid-gap. (zg~ cut in oxide thermally grown on diffusion regions. These have a large effect on source drain leakage Very often this oxide is thicker than the gate oxide currents as they are very effective generation- and requires a longer etching time so that the final recombination centres. These centres are most hole in the gate oxide may be of larger area than effective when the surface is in a depleted condition. the original mask imperfection. At metallization, The effect of aluminium sintering or other "low" aluminium will pass into the gate oxide hole leaving
330
W. E C C L E S T O N
and M. P E P P E R
a metal-semiconductor junction to the comparatively lightly doped bulk material. This produces a Schottky barrier characteristic and is not immediately apparent from the M O S T characteristic. A second form of weakness occurs on gates which are subjected to a light etch after growth. Whilst this has the advantage in removing a large fraction of any mobile contaminant from the oxide it causes weak dielectrics if fast etching imperfections are present. (20~ Normally there is a safety factor between the dielectric strength of an oxide around 1000A thickness and stressing fields found during life. T h e stressing fields are seldom greater than 3.106 V cm -1 where dielectric strengths of the order of 2.107 V cm -1 have been measured on 1700 A thermal oxides produced with dry oxygen at 1000°C. Results of destructively breaking down capacitors are shown in Fig. 3.
~orm
Log (yield) = --koz Aox where Aox is the area of gate oxide and kox is a process constant associated with the probability of not finding a defect in a given area of the gate oxide. It has been found by the authors that for a given set of circuit layout rules one can write an approximate relationship of the form Achip
kAox.
=
Whilst this is only approximate (k varying by less than 20 per cent), we can predict a yield relationship for chips of the form log (yield of chips) ~ A chip provided that random dielectric defects are the yield determining factor. This relationship for a given average defect density across a slice gives a
I00 90 80 7O 6o "E 5O o_ 40 50 2O
X
/
I0 0
,
z
~
~,
5
s
~
s
Electric field strength,
9
,o
J,
~z
Is
;4
,s
V x l O s cm -I
FIO. 3. A n Ogive plot showing the percentage of capacitors having dielectric strength less than each value on the horizontal axis.
Regions of low dielectric strength can also exist even when oxide thinning by etching is not carried out. T h e cause of these imperfections is not clear but they appear to occur randomly across a slice. It can be demonstrated that for a truly random distribution of oxide defects the yield of good gates might be expected to follow a relationship of the
very drastic drop of yield with area and makes L S I difficult. It is the essentially random nature of the defects which causes this to be true and is the main reason why dielectric imperfections become important for large chips. Whilst a number of factors may affect dielectric strength, such as the presence of steps in the silicon, or oxide steps,
(i) Contact resistance. (ii) Aluminium breaks or open circuit contacts. (iii) High VT, check at 3. (i) Gate dielectric short either to diffusion or substrate or weak gate protection diode (see 4). (ii) Gate protection diode has avalanche voltage less than spurious M O S T threshold (not a failure mode). (i) Contaminant in gate oxide. TVas may drop with time under these conditions. (ii) Ionic conduction on oxide surface. (iii) Punch through, see 5. (iv) Gate to source short produced by 2. (v) Possibly O[C gate electrode. (i) Weak diode requires more detailed visual examination. (ii) Gate to substrate short probably produced at 2. (i) Gate to drain short produced at 2 but missed at 3 because of measurement condition. (ii) Overlapping metal (see Fig. 7) (iii) Further examination required, e.g. (S.E.M.). (iv) Punch-through (if Vp VT then would have been seen at 3). T h e effect is dependent on the value of V~. Examine family characteristic. As 5. (i) Contact resistance removed by "burning in". (ii) As before, see 1. (iii) Instability through walk-out of drain diode and consequent reduction of channel length.
(i) RDS varies with VD. (ii) O/C between S and D. (iii) RDS high but independent of VD.
As 5. (i) R o s now independent of VD. (ii) O/C between S and D. (iii) RDs normal but reduced in value.
1D and AVD2.
(ii) Field induced junction (light sensitive). (iii) Weak diode with avalanche. (iv) No avalanche but leakage of form
The measurements refer to an M O S T device with access to gate, source and drain and with a gate protection diode connected to the gate which is suitable for measuring TVass.
6. BVsos 7. Rns (repeat)
(Drain breakdown voltage)
Source to all other terminals. As 1.
Drain to all other terminals.
5. BVDss
(i) s/c.
(i) Leaky but shows avalanche. (ii) s i c
Gate to substrate only.
4. B VGsub0 (Breakdown voltage of gate protection diode)
(True M O S T threshold voltage)
3. TVas
(i) High TV~s. (ii) High current below TVas. (iii) Low value and independent of gate potential. (iv) S/C. (v) Apparently very unstable.
(ii) Avalanche and walkout.
(i) s/c.
Cause
Symptom
Gate and drain to source and substrate. Flick from previous measurements (TVass) without changing voltage.
(Spurious M O S T threshold voltage)
2. TVoss Gate to all other terminals--current level to be ascertained from circuit requirements.
Va = - 2 0 V . la = 0'1 mA and 1 mA.
1. RDs
(Channel resistance below pinch-off)
Measurement conditions
Parameter
Table 1. Diagnostic table
o~
I~
O
O
~ F'
O
©
332
W. ECCLESTON
a major cause is the presence of particulates in the gate areas. The conditions of aluminium sintering are also considered to be important. (21) A number of techniques exist for decorating defects. A reproducible technique is electrophoretic decoration with copper. (22, 2a) There is no information at present directly relating decorated sites to regions of low dielectric strength. The study of oxide defects has been largely ignored but will become increasingly important with the advent of large-scale integration. 4. IONIC C O N D U C T I O N O N OXIDE SURFACES
Currents can pass between the gate and drain or source of an M O S device through mobile ions on the surface of the oxide. (a4~ The effect is very dependent on the ambient gas and humidity. It can be reduced by dry encapsulation or by cooling to be low 0°C. A more dramatic example of this effect is obtained when a misaligned gate leaves exposed gate oxide at the end of the channel (Fig. 4). If the gate is subjected to a heavy negative bias for a few seconds before examining the transfer characteristic of the device, the latter shows a large amount of leakage below the threshold voltage. This is not leakage over the top of the oxide between source and drain but negative charge on top of the oxide inducing carriers in the semiconductor surface and thereby an inversion layer between source and drain. T h e relaxation time of this channel conductance is very dependent on the
and M. PEPPER
ambient humidity. 1~5) Figure 5 shows the change of source-drain leakage current with time. The characteristic is composed of two individual characteristics. T h e leakage between source and drain at the end of the channel is superimposed on the more normal threshold characteristic of the remaining part of the channel. This effect provides a very good test for the quality of encapsulation as it is dependent on humidity. It can be eliminated by cooling the device to liquid nitrogen temperature. Alternatively, a device which has been polarized as described, by a large negative bias, can be held, if cooled, in this conducting condition for many hours. To overcome this effect on practical M O S devices it is necessary to extend the gate metal so that it terminates on thick oxide away from the channel of the device, and where, because of the greater oxide thickness and resulting lower oxide capacitance, insufficient charge will accumulate to cause inversion between source and drain. 5.
SPURIOUS MOST LEAKAGE
In circuits containing M O S devices the voltage required to turn on a device will be dependent not only on the inherent turn-on of the device but also on the respective potentials of the source and drain. Under conditions where the source of a device is at a more negative potential than the substrate, the source region will be reverse biassed. This increases the voltage to be applied to the gate to cause the device to turn on. For this reason it is often necessary
Exposea gate oxide
Diffusion window -
~
-
Diffusion window
Gate aluminium FIO. 4. A misaligned gate metal likely to cause gross s o u r c e - d r a i n leakage currents.
M O D E S OF F A I L U R E OF MOS D E V I C E S
333
< =k
5
6
5
4
3
2
|
v~, v rio. S. The effect of a misaligned gate on the threshold voltage characteristics of a single MOS device. The characteristics measured between source-substrate and gate-drain. Curves (A), (B), (C), (D), (E) and (F) were measured at 0'5 min intervals after applying a large pulse to the gate. to apply gate voltages greatly in excess of the inherent turn-on voltage of the device. On occasions this voltage may become sufficiently high to cause inversion of silicon under thick oxide and thereby a shorting path between adjacent diffusions. This effect is known as the "spurious M O S T " . It can be eliminated by increasing the oxide charge associated with the thick oxide or by increasing the oxide thickness. Both of these solutions have difficulties associated with them. As the thick and gate oxide see much the same processing steps towards the end of the process, they will have similar levels of surface states and oxide charge. Increasing the thickness of the initial oxide can cause metallization problems. A ratio of ten between gate and thick oxide seems to be the maximum possible without having low dielectric breakdown gate oxides or very large thick oxide steps for the metallization to negotiate. We can write down a general expression for the ratio of
the gate (V r) and thick oxide (VT') threshold voltages:
= Xo__' Xo where xo x 0'
(1Xo!
= gate oxide thickness = thickness of spurious M O S T oxide ~MS = gate metal-semiconductor work function difference 9'MS = work function difference of spurious MOST 9B = potential difference between real and intrinsic fermi-levels. This expression is obtained by applying Gauss' Law to both oxides, assuming the surface states and oxide charge induce the same amount of charge in the semiconductor and metal. Some difficulty is experienced in defining the
334
W. E C C L E S T O N and M. PEPPER
measuring conditions of the spurious M O S T turnon voltage. The transconductance of the spurious M O S T is given by equation (3). In the case of a thick oxide the capacitance will be a factor of 10 below that of a gate, and the aspect ratio in a circuit will be very poorly defined but generally less than unity. This gives a very low, ill-defined gin. In consequence great care must be taken in defining the current level at which the spurious M O S T is measured as a difference of a factor of 10 in current will give a turn-on difference of many volts. The equation (2) gives a value of V'T of 30 V for an oxide ratio of 10, unity aspect ratio, and a threshold voltage of 4.5 V on 8 ~cm n-type silicon. This would appear to be a sufficiently high value to overcome undesirable spurious effects. For a 2 V threshold device made on 100 orientation silicon, however, and for the same basic parameters, the spurious turn-on voltage is 9 V which could be a cause of difficulty. This can be overcome at the expense of packing density, either by including n ÷ diffusions beneath aluminium rails on thick oxide, or by increasing the distance between adjacent diffusions to reduce the aspect ratio and hence gm of the spurious MOST. 6. P U N C H T H R O U G H
As voltage is applied to the drain of a M O S T the depletion region will extend and avalanche will occur when the critical field is reached. The extent
of the depletion region at avalanche depends on the impurity concentration of the bulk. When the depletion region extends to the source before avalanche, "punch through" will take place. The situation is depicted for a p-channel M O S T in Fig. 6. The field between the source and drain will lower the potential barrier for holes at A. Holes will then be injected into the high field region at B. They may appear there in sufficient numbers to reduce the effect of the applied field on A and thereby reduce any further lowering of the barrier at A. Under these circumstances the current from the source to the drain will be space charge limited, as in MOS devices the density of acceptors and donors in the channel region is low. The current-voltage relationship at punch through is expected to be of the form IDeA VD ~
where AVD is the excess voltage over the punchthrough value. (A simple treatment of this condition is given by Jonscher. (26)) The method of calculating the relationship between punch-through voltage, channel length and bulk impurity concentration depends largely on the form of the diffusion. To determine whether the one-sided step junction or the linear graded junction applies, a "rule of thumb" method has been described by Grove. <6) The diffusion length is (2~/Dt), where D is the diffusion coefficient of the impurity at the temperature of drive-in, and t is
Drain CB.
Source
EF. . . .
FIG. 6. D i a g r a m m a t i c r e p r e s e n t a t i o n of t he p u n c h - t h r o u g h condition.
MODES OF FAILURE OF MOS DEVICES
335
or "roll on". The reverse breakdown voltages of planar diodes increase with increase in reverse voltage. Typically for 8 ~ c m n-type silicon an initial avalanche voltage of 40 V will increase to 50V on increasing the applied voltage. The avalanche characteristic is initially sharp, becoming rounded after "walk-out". On removing the voltage across the diode the breakdown voltage remains at the final high value. Removal of the passivating oxide from an unstressed junction removes also the walk-out, the measured value under these conditions being nearer to the "walkedwBI I+1 ~ l + out" value. Clearly the instability is associated qCB with the presence of the passivating oxide. Increase where CB is the concentration of donors or aceep- of avalanche voltage would be expected from either tors and ~B1 and ~B2 are the potential differences ionic movement across the junction or phosphorus between real and intrinsic Fermi levels in the glass polarization. The latter does not, however, explain the presence of the effect in the absence of diffused junction and bulk silicon respectively. phosphorus stabilization. At temperatures of 77°K Under conditions of punch through: the effect occurs at a similar speed to that at room (a Sq CB] temperature and this is incompatible with the 2KKo ] = Vv (4) observed temperature dependence of the relaxation where a is the channel length and Vv is the punch times of ions. Ionic conduction on top of the oxides can be discounted for this reason, and because the through voltage. We have neglected [ ~ g l [ + [ ~?B2[ as this must be less than the energy gap of walk-out characteristic is still present in the presilicon (1.1 V) and for most practical purposes sence of an aluminium guard-ring on the oxide will be significantly less than Vv. a in this equation above the diffusion perimeter. The effect has been noted (~7, ~8~on n÷p junctions is not the "drawn" spacing of the source and drain but that less the sideways spread of the diffusions. and p+n. The walk-out on the p+n junctions For 8 ~cm silicon a 10 ~m true channel length (p-channel devices) is at least an order of magniwill give a punch-through voltage of 65 V but for tude greater than on n÷p. A possible explanation 3 ~m we obtain a value of 5 V. This punch-through of this effect has been given by Hara et al. c2s~ is the fundamental limit on the source drain The avalanching junction contains carriers of both spacing. The resistivity of the silicon can be types and these will be present with sufficient decreased to increase the punch-through voltage, energy just inside the silicon surface to enter the but this will increase junction capacitance, decreas- oxide, by negotiating the electron affinity of the ing circuit speed and increasing the device thresh- semiconductor. It is not clear whether the energy hold voltage. The punch-through voltage is very levels into which the carriers enter are always dependent on the voltage applied to the gate. This present or are in some way created by the applied is particularly true for a "pinched-off" channel. fringing field. The effect can be controlled by use Gross distortion of the device characteristics may of a field electrode around the junction perimeter. occur at gate voltages above threshold. When the Some recovery is seen if the device is heated for high voltage drain characteristics is apparently long periods of time. limited by avalanche, punch through may still The instability is not normally classed as a mode increase leakage currents between source and drain of failure but because it involves depletion layer for lower drain voltages. widening along the channel it must be allowed for in calculating source drain spacings. Hara et al. 7. UNSTABLE DIODE AVALANCHE VOLTAGE indicate a 30 per cent change in channel length of This effect is present on MOS devices and is a 4 izm device, which becomes only a 1 per cent known by a variety of names, such as "walk-out" change in a 200 ~m device. The amount of the time of the drive-in. If the width of the depletion region is greater than the diffusion length then the one-sided step junction approximation applies. If the width of the depletion region is less than the diffusion length the linear graded junction approximation is used. For most practical MOS structures the one-sided step junction represents a very good approximation. From the application of Poisson's equation to this type of impurity profile the width W of a depletion region can be shown to be:
W=/2KKo(I
VD)
336
W. E C C L E S T O N
walkout is, of course, a strong function of the bulk impurity density. On 2f~cm n-type material the walk-out is reduced to a few volts for levels of positive charge in the oxide between 1011 and 101~ e- cm-L 8. OTHER CAUSES OF DIODE LEAKAGE
8.1 Irregular oxide photo-engraving The avalanche voltage both before and after walk-out is a function of the field across the depletion region of the junction. This field can be increased by a junction curvature either normal or parallel to the surface of the silicon. Breakdown at curvature normal to the surface will occur in planar technology owing to the cylindrical nature of the diffusion profile. Curvature in the plane of the surface can be caused by sharp corners produced intentionally or accidentally on the oxide windows. 8.2 Silicon defects Defects within the area of the depletion region will cause high leakage in the reverse characteristics. This will only occur when the defect is situated within the depleted region, so that leakage currents at low reverse voltages may be normal36) A large amount of work has been carried out on silicon defects, most of which is applicable to M O S devices. These defects can be process induced or can be present in the initial material.
and M. P E P P E R
To reduce process induced defects the following general rules apply: (a) Avoid mechanical damage, particularly to the edge of the slice. (b) Wherever possible keep processing temperatures below 1000°C. (c) Wherever possible lie slices flat during high temperature operations. Because defects are likely to be grouped around the edge of the slices the loss of chips from this area will be greater than that at the centre. (29-31~ For a given average density of defects, therefore, the yield in the centre will be higher than for spatially random defects. The relationship between yield of good chips and chip area will be of the form which gives greater yields than expected for a logarithmic distribution. 8.3 Field induced junctions Care must be taken in terminating the metallization of source and drain. This can act as a relief electrode and produce an extension of the true diffused junction beneath the metal as shown in Fig. 7. A new junction is produced at the edge of the metal which may have a lower breakdown voltage than that of the true diffused junction. (6) Increasing the voltage across the junction causes the conducting channel to pinch-off after the initial avalanche occurs. The field induced junctions Light
FIG. 7. The condition at a source or drain likely to lead to field induced junctions and spurious diode leakage.
FIc. 8. Incomplete coverage of an oxide step due to the position of the filament used for evaporation. T h e width of the aluminium stripe is 12 ~.
facing page 336
Fie;. 9. T h e effect of e t c h i n g a n a l u m i n i u m s t r i p e on top of a c r e v i c e i n a d e p o s i t e d o x i d e o n a first l a y e r s t r i p e of a l u m i n i u m .
M O D E S OF F A I L U R E OF MOS D E V I C E S may be light sensitive and care must be taken to measure them under dark conditions in assessing their importance. They are, of course, a major source of difficulty in self-scanned silicon diode photo-arrays where such a relief electrode may be used to reduce leakage currents and thereby improve sensitivity. This is only possible at voltages below the breakdown voltage of the field induced junction. At quite a low voltage the field induced junction will avalanche and pinch-off. At higher voltages much higher leakages will be present, and any benefit from the relief electrode will be negative, especially as in the case of self-scanned arrays where light is necessarily present. 9. INADEQUATE CONTACTS Low resistance contacts between the metal and diffusions is a normal requirement of MOS circuits. This is achieved by photo-engraving oxide regrown on the diffusion before metallization. The stages are: (a) Apply resist, expose and develop. (b) Etch regrown oxide. (c) Remove resist by using an oxidizing medium. (d) Evaporate metal. (e) Photo-engrave metal. (f) Anneal for 10-30 rain at 400-500°C in inert ambient. The etching of the regrown oxide can cause problems on boron diffused regions. During deposition of the boron a silicon-boron phase is produced in the windows. Upon oxidation this produces a region in the oxide of low etch rate next to the silicon. In removing this region, gross undercutting of the remaining oxide will occur, especially when this contains phosphorus for stability purposes. Ellipsometer investigations indicate that this low etch rate oxide is within 100 A of the silicon and can be removed by successive treatment of the slice in hydrofluoric acid, followed by boiling nitric acid, followed by hydrofluoric acid. (The hydrofluoric acid must, of course, be diluted to prevent removal of thicker oxides on the remainder of the circuit.) When the slow etching phase has been removed, the photoresist has still to be removed. This is carried out using an oxidizing medium, and will cause some oxide to be grown in the contact hole. This may only be 20 A in thickness, but is sufficient to cause contact resistance between the metal
337
and the silicon. For this reason it is necessary to heat treat the silicon slice after metaUization. This is normally carried out at 400-500°C. The higher temperature will give more effective contacts and will more effectively annihilate surface states, but will also be a source of oxide defects. ~21~A compromise must therefore be made between the three effects. Reduction of the thin oxide film present after resist removal is obviously advantageous. Care must be taken to ensure effective resist removal, as this is a cause of breaks in aluminium rails on the finished circuits. Contact resistance may distort the M O S T characteristics depending on the electrical conduction processes in the thin oxide film. Smaller contact resistances will produce substrate bias effects, thereby shifting the threshold voltage of the device to more negative values. An effect more important than the change in the value of VT is likely to be that of non-reproducible contact resistances on spatial variations of this parameter. 10. IVIETALLIZATION DEFECTS
As stated previously, failure of a chip to operate may be attributed to open circuit aluminium rails. This can be caused by electromigration 182~ or breaks due to resist left behind after contact photoengraving, or breaks over oxide steps. The latter is particularly severe in MOS devices because of the high ratio required between threshold voltage and the turn-on voltage of the spurious MOST. The extent of aluminium breaks on steps depends not only on the thickness of the metal but also on evaporation geometry. Figure 8 shows a step on an MOS chip facing away from the source of metal. Effective coverage can be achieved by rotating the slice during metallization. The problem of metallizing oxide steps can be particularly severe on processes using deposited dielectrics, e.g. silicon gate, refractory metal gate and multilayer technology. A stated advantage of these processes is to pass metal over active devices, thereby increasing packing density. Deposited dielectric separates the two layers of metallization. Whether the dielectric is produced by chemical deposition or by r.f. sputtering, a crevice is produced. On application of the second metal and photoengraving the result is shown in Fig. 9. This is a likely source of loss of yield or of failure during the life of the device.
W. E C C L E S T O N
338
I I . CONCLUSION Descriptions of the physical basis of the most p r o m i n e n t modes of failure of M O S devices have been described. T h e means of distinguishing between the various causes of failure are discussed. References are given to more comprehensive treatm e n t of p h e n o m e n a . A diagnostic table is presented also which optimizes the sequence of m e a s u r e m e n t for labelling failure modes and describes also the various symptoms. T h e information required b y this table can be added to b y optical and s c a n n i n g electron microscopy as well as b y temperature bias stressing, and the means of interpreting the latter are described in the text.
Acknowledgements--The authors would like to thank Mr. P. C. Newman and Mr. K. J. S. Cave of Allen Clark Research Centre for critically reading the manuscript. We would also like to thank the directors of the Plessey Company for permission to publish this review.
REFERENCES
1. D. R. KERR, J. S. LOGAN, P. J. BURKHARDTand W. A. PLISKIN, I B M f f . Res. Dev. 8, 376 (1964). 2. P. BALKand J. M. ELDRIDOE,Proc. 1EEE57, 9, 1558 (1969). 3. J. M. ELDRmCE and P. BALK, Trans. N . Y . Acad. Sci. 32, 1, 13 (1970). 4. W. ECCLESTONand M. PEPPER. (To be published.) 5. S. R. HOFSTEIN, I E E E Trans--ED 13, 222 (1966). 6. A. S. GROVE, Physics and Technology of Semiconductor Devices, John Wiley, New York (1967). 7. E. H. SNow and B. E. DEAL, ~. e2ectrochem. Soc. 113, 263 (1966).
a n d M. P E P P E R 8. E. H. SNOW and M. E. DUMESNIL,J. appl. Phys. 37, 2123 (1966). 9. S. R. HOFSTEIN,Solid State Electron. 10, 657 (1967). 10. A. MANY, T. GOLDSTEINand N. B. GROVER, Semiconductor Surfaces, North Holland, Amsterdam (1967). 11. A. G. REVESZ and K. H. ZAININGER,R C A Rev. 29, 1, 22 (1968). 12. E. KooI, The Surface Properties of Oxidized Silicon, Philips Technical Library (1967). 13. M. PEPPER and W. ECCLESTON.(To be published in Thin Solid Films.) 14. P. BALK,Buffalo Meeting of Electrochem. Soc. (1965). 15. J. T. WALLMARKand J. H. SCOTT, R C A Rev. 30, 335 (1969). 16. D. FROHMAN-BENTCHKOWSKYand M. LENZLINGER, ft. appl. Phys. 40, 3307 (1969). 17. R. E. OAKLEY,Electron. Lett. 7, 4, 89 (1971). 18. N. ST. J. MURPHY, F. BERZ and I. FLINN, Solid State Electron. 12, 775 (1969). 19. J. L. PAUTRAT and J. C. PFISTER, Solid State Commun. 8, 1173 (1970). 20. A. D. LOPEZ,ft. electrochem. Soc. 113, 89 (1966). 21. N. J. CHOU, J. H. ELDRIDGE,ft. electrochem. Soc. 117, 10, 1287 (1970). 22. P. J. BESSERand J. E. MEINHARD,Proc. Symp. Manufacturing In-Process Control and Measuring Techniques for Semiconductors, Phoenix, Arizona (1966). 23. W. J. SHANNON, R C A Rev. 31,431 (1970). 24. W. SHOCKLEY,W. W. HOOPER, H. J. QUEISSERand W. SCHROEN, Surface Sci. 2, 277 (1964). 25. M. PEPPER. (Unpublished.) 26. A. K. JONSCHER, Principles of Semiconductor Device Operation, Bell (1969). 27. R. W. GURTLER,I E E E Trans. EL) 15, 980 (1968). 28. H. HARA, Y. OKAMOTOand H. OHNUMA, Japan ft. appl. Phys. 9, 9,1103 (1970). 29. G. H. SCHWUTTKE,Microelectronics & Reliab. 9, 5, 357 (1970). 30. B. T. MURPHY, Proc. I E E E 52, 1537 (1964). 31. G. E. MOORE, Electronics 43, 4, 126 (1970). 32. J. R. BLACK,I E E E Trans. ED 16, 4, 338 (1969).
Pergamon Press 1971. Vol. 10, pp. 325-338.
Printed in Great Britain
MODES OF FAILURE OF MOS DEVICES W. ECCLESTON* a n d M. PEPPER
The Plessey Company Limited, Allen Clark Research Centre, Caswell, Towcester, Northants., England A b s t r a c t - - A review is presented of the physical basis of loss of yield and failure of integrated
circuits containing MOS devices. The causes of variations in both threshold voltage and other parameters are described. The effects of oxide and silicon defects on chip yield and reliability are discussed. Also included is a diagnostic table summarizing the means of distinguishing between the various modes of failure. All the physical effects are described with reference to p-channel aluminium gate devices. Extension of the results to other forms of MOS device should in most cases be obvious, as should the recognition of the phenomena on capacitance-voltage curves.
INTRODUCTION
THE fabrication of single-layer aluminium gate M O S integrated circuits requires four photoengraving operations: one diffusion, three oxidations and a metallization. W h e n compared with bipolar technology this represents a considerable reduction in process complexity and thus implies a higher yield and lower cost. By its nature, however, M O S has modes of failure due to phenomena which are often considered to be of secondary importance in bipolar technology. Most of the phenomena are associated with the properties of thermally oxidized silicon. A vast amount of information is available on the properties of the silicon dioxide-silicon system. Relating these properties to the electrical behaviour of M O S devices is not always easy. T h e purpose of this review is to summarize all the phenomena both in the literature and found by the authors, which are responsible for the failure of M O S devices. T h e physical concepts are presented with a reference to more comprehensive treatments elsewhere in the literature. W h e r e it has been necessary to discuss concepts not explicitly treated in the literature, then a more complete discussion is presented. T h e modes of failure are all described, for convenience, with reference to p-channel aluminium gate devices.
Extension of the concepts to n-channel or autoregistered devices should in most cases be obvious. 1. FIELD-DEPENDENT T H R E S H O L D
VOLTAGE 1.1 Mobile ions T h e threshold voltage of an M O S device is that voltage required to produce an inversion layer in the silicon and thereby a conducting surface layer between the source and rain. This voltage is determined by the amount of charge associated with the oxide and interface, as well as by the resistivity of the silicon and the work function difference between the metal and the underlying silicon. T h e amount of charge associated with the oxide can be affected by the presence of impurities such as alkali ions. These will have a positive charge and will therefore tend to increase the threshold voltage of p-channel devices. T h e effect of ions moving in the oxides of M O S structures can best be understood from a simplified model depicted in Fig. 1. A strip of charge, Q, is considered to exist somewhere in the oxide parallel to, and distance x from, the metal electrode. T h e total oxide thickness is x 0. By application of Gauss's Law to this situation it is readily shown that X
Q s c = Q xo
(1)
and
*Now at Dept. of Electronic and Electrical Engineering, University of Liverpool, U.K. 325
QM = Q (*0--x) X0
(2)
326
W. E C C L E S T O N i
and M. P E P P E R
(c) If the surface of the oxide can be converted to a form which will render ions immobile, I I on then ions will, upon entering this region, be rendered harmless, as x in equation (l) will X be small. This is the basis of "phosphorus o (v~) stabilization. ''(l-a) T h e surface of an oxide is Xo stabilized by subjecting it to a phosphorus Oxide diffusion. During the deposition ions will migrate to the surface and become "locked" _~ _ _ in position because of the presence of deep trapping sites. This also applies to ions which can enter from the ambient. In this condition FIG. 1. The effect of charge within a dielectric on the (from equation (1)) the ions have a minimal semiconductor surface charge for an MOS structure. effect on the value and stability of the threshFrom Gauss' Law hold voltage. T h e relaxation times for ionic instability can be of the order of a few milliseconds at 200°C. (4, a) T h e direction of threshold voltage shift for a given polarity of bias is always the same whether the ions are where g = dielectric constant of oxide, K0 = dielectric positive or negative (less negative threshold constant of free space, also Qs~+QM=Q, voltage for negative stress on the gate). T h e hence equations (1) and (2) are easily proven for VM = 0. application of negative voltage to a gate electrode causes movement of mobile positive oxide charge to the gate. From equation (1) this will produce a less negative threshold where Qsc and QM are the charges induced in the voltage on p-channel devices, as the surface semiconductor and metal respectively by the will be less accumulated and nearer to inverpresence of the charged strip Q. sion. If the ions were negative, with negative As the strip of charge moves nearer to the metal bias applied to the gate electrode, they will the charge induced in the semiconductor becomes move towards the semiconductor inducing less, and when the strip of charge is coincident positive charge in the substrate (or removing with the metal the induced charge in the substrate negative charge). This will cause the semiconis zero. ductor surface to be less accumulated and will It is known that mobile charge tends to migrate reduce the voltage required to produce inverduring processing to the surface of the oxide. This sion. Hence both positive and negative ions has three important implications: will, for a given bias on the gate, cause the (a) Under negative biassing at temperature the same direction of change of threshold voltage. shift in the threshold voltage is less than one T h e field dependence of relaxation times can c4, 5) would expect from a uniform distribution of ions, but larger shifts will be seen for positive be of the form: temperature bias stressing. It is not always possible to do the positive biassing as it is now common to include gate protection In the absence of an electric field the migration diodes, to protect the gate against a large of ions is governed by the diffusion equation: voltage build-up. These diodes will under 02N ON positive gate conditions become forward D Ox2 Ot biassed. (b) Etching a thin layer of oxide after growth where N is the ionic concentration. can often remove a high percentage of the T h e diffusivity D can be represented by: contaminant. This can, unfortunately, lead to D = Doe-WqlkT another failure mode described in Section 3. • Metal
[ V~ I
f
=0
MODES
OF FAILURE
OF MOS
DEVICES
327
I I
I
--,~---u
P
Distance
FIG. 2. T h e superposition of a field on a potential well.
where D Ois constant and W is the activation energy for diffusion. In the presence of an applied electric field (E), the potential barrier to ionic motion becomes modified, as shown in Fig. 2. If E ~ k__T the q~ diffusion equation becomes:
aN
02N
ON
Ot -- D -~xxz--[~E(x)] O--x
where ~t is the ionic mobility. The solution of this equation is complex as the field across the oxide is not constant but is modified by the space charge of the ions themselves and changes of structure in the oxide. (e) For these reasons analysis of ionic migration in MOS structures is not straightforward. Activation energies can be dependent on the details of oxide preparation. 1.2 Polarization of phosphorus The use of phosphorus as a stabilizing agent is well known and documented. (x-3) It is unfortunate, however, that it can give rise to a qualitatively similar form of instability to that of mobile ions.(7, 8) This instability of threshold voltage is caused by polarization of the phosphorus doped oxide layers. The application of field and temperature to the device causes strips of charge to appear at the metal-glaze interface and at the glaze-oxide interface. From Fig. 1 and equation (1) it can be seen that although the two strips of charge should be equal and opposite in amount, they will have different effects on the surface potential of the
silicon. It is therefore important to make the glass layer a small fraction of the total oxide thickness, consistent with effective gettering of impurity ions. The amount of phosphorus included in the glass is also important. The direction of threshold voltage shifts is the same as for ionic instability, for a given polarity of stressing voltage. It is, however, distinguishable from positive mobile ions by the ability of this polarization to move the threshhold voltage through zero. This is not possible with mobile ions as they are usually positively charged, as is the net charge associated with surface states and fixed oxide charge. 1.3 Slow trapping A widely experienced mode of behaviour seen on MOS devices is the threshold voltage becoming more negative on application of negative bias to the gate. (9-11) This is the opposite type of shift to that caused by mobile ions and phosphorus polarization. It is usually caused by changes in the occupancy of traps a few angstroms from the oxide-silicon interface. Carriers from the silicon surface can enter the traps by tunnelling. These have long relaxation times and will induce charge entirely in the silicon surface, altering the threshhold voltage of the device. This phenomenon has been known since early work on the free surfaces of semiconductors, (1°) and is particularly severe between deposited oxides and semiconductor surfaces. In this case the instability has relaxation times of seconds and can be seen as hysteresis on slowly swept device characteristics or capacitancevoltage curves. These traps are differentiated from
328
W. E C C L E S T O N and M. PEPPER
faster interface states by their response time. (In the case of fast surface states relaxation times of 10.8 sec 112~ are not unusual.) It is, of course, possible for the two forms of instability to be present simultaneously and cases of fast ionic instability followed by a slow recovery due to slow trapping have been reported. (9~ Slow trapping is increased by subjecting the device to ionizing radiation; for example, 1 keV electron bombardment will create such traps. Fortunately much of this instability can be removed by low temperature (<600°C) anneals in the presence of moisture or hydrogen, or by careful choice of aluminium sintering conditions, n3, 14~ A not dissimilar effect is obtained with oxidenitride sandwich gate dielectrics. The different conductivity of the two dielectrics results in a build-up of charge at the interface between them and this will cause threshold voltage shifts. This is the mode of action of the MNOS, a variable threshold device. To obtain maximum switching speed in this device, the current through the oxide layer should be controlled by tunnelling from the silicon, a5-17) This necessitates a very thin oxide layer and the behaviour of this type of device is quantitatively very similar to that expected from slow trapping.
The temperature dependence of the effect is not known, nor is the cause. 2. SPATIAL VARIATION IN THRESHOLD VOLTAGES
2.1 Mobile ions and other field dependent effects Variations in the concentrations of mobile ions, slow traps or phosphorus polarization can cause threshold voltage variations across a slice. These can be quantified by application of field and temperature to the MOS gates. In the case of mobile ions the spread of threshold voltage is reduced after negative biassing at temperature. The spread of threshold voltages is likely to become worse if the cause of the variations is phosphorus polarization. The instability caused by slow traps is very dependent on the average density of the traps and their energy level. It is not possible to generalize about the effect of these on spatial variations of threshold voltage.
2.2 Effect of resistivity variations Crystals of silicon grown by the Czochralski technique show a radial distribution of resistivity. This affects the amount of charge which needs to be applied to the gate of the device to pass from the normally accumulated condition (on n-type substrates), to inversion. For p-channel devices 1.4 Mobility instability the convention widely used for defining inversion It has been demonstrated by Murphy et al., (18~ is that surface potential at which the surface is as using surface Hall effect measurements, that appli- p type as the bulk is n type. This definition can be cation of a field to the gate of a device can cause a used to calculate the effect of resistivity variations change in the carrier surface mobility with time. on threshold voltage. The surface potential is This is the true surface mobility defined as assumed to be 2~B where ~B is the potential difference between real and intrinsic fermi levels. da It has been found by the authors that these caldQsc culated variations are often larger than those found where a is the surface conductance. This quantity in practice. Furthermore, experimental variations is different from the field effect mobility which is do not have the spatial variations expected from resistivity changes across a slice. An explanation of defined as d~ this may be obtained from the work of Murphy ~tQg" et al., (lsl where large changes of surface mobility The latter includes the effect of trapping in surface are measured at threshold. This could indicate states and is not a true mobility, but a method of that the surface conductance is limited more by combining all the factors reducing the surface con- mobility than carrier concentration and thus the ductance into one term having dimensions of effects of bulk resistivity variations are rendered mobility. Since Murphy's technique measures true negligible. surface mobility the effect must be different from that of slow trapping, although it is in the same 2.3 Variations in fast surface state density After oxidation there are wide variations in direction for a given sign of voltage stress and field.
M O D E S OF F A I L U R E OF MOS D E V I C E S surface state density across the silicon surface. A significant reduction is obtained by optimizing the aluminium sintering conditions, or by one of several other low temperature heat treatments. (m I f these surface states are not completely removed, then because of the initial spread in their density one might expect variation in device parameters. These surface states may be important not only from the point of view of threshold voltage, but also in determining the value of
( dI, I g~ = ~ / v a where Ia is the drain current and Vg is the gate voltage. The simple MOS equation below pinchoff:
~a= ~Co![(v~-v~)v~-?] gives dla b - ~Co- va dVg
(3)
where C O = the capacitance per unit area of the gate b = the aspect ratio of the channel defined as a
the ratio of channel width to channel length Va = the applied source drain voltage and = ~Fe is the field effect mobility defined
329
temperature heat treatments on mid-gap states has not been studied in detail. The indications are that this state is less affected by the aluminium sintering conditions and hence may have a large effect on threshold voltage variations. Because of its energy, however, this state is unlikely to have a large effect o n gin.
The effect of the conduction band surface state on threshold voltage is not easy to ascertain. Our knowledge of the surface states at the silicon interface only extends to being able to assign a density and energy to a state. No obvious method exists for ascertaining whether the states are donor-like or acceptor-like. For inversion of n-type silicon a donor state at the conduction band edge will be positively charged (as it will be unoccupied by electrons) and could have a pronounced effect on threshold voltage. If it is an acceptor, however, it will be neutral and will remain so in depletion and inversion with little effect on threshold voltage. The normal convention for defining surface state density and oxide charge assumes that the conduction band state is an acceptor and the valence band state is a donor. It should be noted that, at present, this is no more than a convention. Irrespective of its type, the conduction band state will have little effect on gm for a given value of
(v~-v~,). 3. GATE OXIDE LEAKAGE
Gate leakage currents can be caused by gate protection diffusions with weak diode characteristics or by imperfections in the gate or other oxides. d~ earlier as dQg" The case of weak junction characteristics is described in Section 8. Dielectric imperfections can We can rewrite the expression for field effect be caused by a large number of factors. One of the mobility in the form: most easily recognized is that due to ineffective photoresist masking at contacts photo-engraving. d6 d6 Imperfect photo-engraving masks may contain ~FE -- dQg -- d(Qss+Osc)" pinholes or spots. Depending on the type of I f Qss is the sum of fixed charge and surface photoresist used these may cause small regions of state charge then dQss is the change of charge in the gate oxide not to be protected, which are etched surface states. For a state near the valence band away during the normal etching of contacts. The d Q s s will be finite and hence ~ B will be reduced. contacts are, in the case of aluminium gate devices, It is known that there exist states in mid-gap. (zg~ cut in oxide thermally grown on diffusion regions. These have a large effect on source drain leakage Very often this oxide is thicker than the gate oxide currents as they are very effective generation- and requires a longer etching time so that the final recombination centres. These centres are most hole in the gate oxide may be of larger area than effective when the surface is in a depleted condition. the original mask imperfection. At metallization, The effect of aluminium sintering or other "low" aluminium will pass into the gate oxide hole leaving
330
W. E C C L E S T O N
and M. P E P P E R
a metal-semiconductor junction to the comparatively lightly doped bulk material. This produces a Schottky barrier characteristic and is not immediately apparent from the M O S T characteristic. A second form of weakness occurs on gates which are subjected to a light etch after growth. Whilst this has the advantage in removing a large fraction of any mobile contaminant from the oxide it causes weak dielectrics if fast etching imperfections are present. (20~ Normally there is a safety factor between the dielectric strength of an oxide around 1000A thickness and stressing fields found during life. T h e stressing fields are seldom greater than 3.106 V cm -1 where dielectric strengths of the order of 2.107 V cm -1 have been measured on 1700 A thermal oxides produced with dry oxygen at 1000°C. Results of destructively breaking down capacitors are shown in Fig. 3.
~orm
Log (yield) = --koz Aox where Aox is the area of gate oxide and kox is a process constant associated with the probability of not finding a defect in a given area of the gate oxide. It has been found by the authors that for a given set of circuit layout rules one can write an approximate relationship of the form Achip
kAox.
=
Whilst this is only approximate (k varying by less than 20 per cent), we can predict a yield relationship for chips of the form log (yield of chips) ~ A chip provided that random dielectric defects are the yield determining factor. This relationship for a given average defect density across a slice gives a
I00 90 80 7O 6o "E 5O o_ 40 50 2O
X
/
I0 0
,
z
~
~,
5
s
~
s
Electric field strength,
9
,o
J,
~z
Is
;4
,s
V x l O s cm -I
FIO. 3. A n Ogive plot showing the percentage of capacitors having dielectric strength less than each value on the horizontal axis.
Regions of low dielectric strength can also exist even when oxide thinning by etching is not carried out. T h e cause of these imperfections is not clear but they appear to occur randomly across a slice. It can be demonstrated that for a truly random distribution of oxide defects the yield of good gates might be expected to follow a relationship of the
very drastic drop of yield with area and makes L S I difficult. It is the essentially random nature of the defects which causes this to be true and is the main reason why dielectric imperfections become important for large chips. Whilst a number of factors may affect dielectric strength, such as the presence of steps in the silicon, or oxide steps,
(i) Contact resistance. (ii) Aluminium breaks or open circuit contacts. (iii) High VT, check at 3. (i) Gate dielectric short either to diffusion or substrate or weak gate protection diode (see 4). (ii) Gate protection diode has avalanche voltage less than spurious M O S T threshold (not a failure mode). (i) Contaminant in gate oxide. TVas may drop with time under these conditions. (ii) Ionic conduction on oxide surface. (iii) Punch through, see 5. (iv) Gate to source short produced by 2. (v) Possibly O[C gate electrode. (i) Weak diode requires more detailed visual examination. (ii) Gate to substrate short probably produced at 2. (i) Gate to drain short produced at 2 but missed at 3 because of measurement condition. (ii) Overlapping metal (see Fig. 7) (iii) Further examination required, e.g. (S.E.M.). (iv) Punch-through (if Vp VT then would have been seen at 3). T h e effect is dependent on the value of V~. Examine family characteristic. As 5. (i) Contact resistance removed by "burning in". (ii) As before, see 1. (iii) Instability through walk-out of drain diode and consequent reduction of channel length.
(i) RDS varies with VD. (ii) O/C between S and D. (iii) RDS high but independent of VD.
As 5. (i) R o s now independent of VD. (ii) O/C between S and D. (iii) RDs normal but reduced in value.
1D and AVD2.
(ii) Field induced junction (light sensitive). (iii) Weak diode with avalanche. (iv) No avalanche but leakage of form
The measurements refer to an M O S T device with access to gate, source and drain and with a gate protection diode connected to the gate which is suitable for measuring TVass.
6. BVsos 7. Rns (repeat)
(Drain breakdown voltage)
Source to all other terminals. As 1.
Drain to all other terminals.
5. BVDss
(i) s/c.
(i) Leaky but shows avalanche. (ii) s i c
Gate to substrate only.
4. B VGsub0 (Breakdown voltage of gate protection diode)
(True M O S T threshold voltage)
3. TVas
(i) High TV~s. (ii) High current below TVas. (iii) Low value and independent of gate potential. (iv) S/C. (v) Apparently very unstable.
(ii) Avalanche and walkout.
(i) s/c.
Cause
Symptom
Gate and drain to source and substrate. Flick from previous measurements (TVass) without changing voltage.
(Spurious M O S T threshold voltage)
2. TVoss Gate to all other terminals--current level to be ascertained from circuit requirements.
Va = - 2 0 V . la = 0'1 mA and 1 mA.
1. RDs
(Channel resistance below pinch-off)
Measurement conditions
Parameter
Table 1. Diagnostic table
o~
I~
O
O
~ F'
O
©
332
W. ECCLESTON
a major cause is the presence of particulates in the gate areas. The conditions of aluminium sintering are also considered to be important. (21) A number of techniques exist for decorating defects. A reproducible technique is electrophoretic decoration with copper. (22, 2a) There is no information at present directly relating decorated sites to regions of low dielectric strength. The study of oxide defects has been largely ignored but will become increasingly important with the advent of large-scale integration. 4. IONIC C O N D U C T I O N O N OXIDE SURFACES
Currents can pass between the gate and drain or source of an M O S device through mobile ions on the surface of the oxide. (a4~ The effect is very dependent on the ambient gas and humidity. It can be reduced by dry encapsulation or by cooling to be low 0°C. A more dramatic example of this effect is obtained when a misaligned gate leaves exposed gate oxide at the end of the channel (Fig. 4). If the gate is subjected to a heavy negative bias for a few seconds before examining the transfer characteristic of the device, the latter shows a large amount of leakage below the threshold voltage. This is not leakage over the top of the oxide between source and drain but negative charge on top of the oxide inducing carriers in the semiconductor surface and thereby an inversion layer between source and drain. T h e relaxation time of this channel conductance is very dependent on the
and M. PEPPER
ambient humidity. 1~5) Figure 5 shows the change of source-drain leakage current with time. The characteristic is composed of two individual characteristics. T h e leakage between source and drain at the end of the channel is superimposed on the more normal threshold characteristic of the remaining part of the channel. This effect provides a very good test for the quality of encapsulation as it is dependent on humidity. It can be eliminated by cooling the device to liquid nitrogen temperature. Alternatively, a device which has been polarized as described, by a large negative bias, can be held, if cooled, in this conducting condition for many hours. To overcome this effect on practical M O S devices it is necessary to extend the gate metal so that it terminates on thick oxide away from the channel of the device, and where, because of the greater oxide thickness and resulting lower oxide capacitance, insufficient charge will accumulate to cause inversion between source and drain. 5.
SPURIOUS MOST LEAKAGE
In circuits containing M O S devices the voltage required to turn on a device will be dependent not only on the inherent turn-on of the device but also on the respective potentials of the source and drain. Under conditions where the source of a device is at a more negative potential than the substrate, the source region will be reverse biassed. This increases the voltage to be applied to the gate to cause the device to turn on. For this reason it is often necessary
Exposea gate oxide
Diffusion window -
~
-
Diffusion window
Gate aluminium FIO. 4. A misaligned gate metal likely to cause gross s o u r c e - d r a i n leakage currents.
M O D E S OF F A I L U R E OF MOS D E V I C E S
333
< =k
5
6
5
4
3
2
|
v~, v rio. S. The effect of a misaligned gate on the threshold voltage characteristics of a single MOS device. The characteristics measured between source-substrate and gate-drain. Curves (A), (B), (C), (D), (E) and (F) were measured at 0'5 min intervals after applying a large pulse to the gate. to apply gate voltages greatly in excess of the inherent turn-on voltage of the device. On occasions this voltage may become sufficiently high to cause inversion of silicon under thick oxide and thereby a shorting path between adjacent diffusions. This effect is known as the "spurious M O S T " . It can be eliminated by increasing the oxide charge associated with the thick oxide or by increasing the oxide thickness. Both of these solutions have difficulties associated with them. As the thick and gate oxide see much the same processing steps towards the end of the process, they will have similar levels of surface states and oxide charge. Increasing the thickness of the initial oxide can cause metallization problems. A ratio of ten between gate and thick oxide seems to be the maximum possible without having low dielectric breakdown gate oxides or very large thick oxide steps for the metallization to negotiate. We can write down a general expression for the ratio of
the gate (V r) and thick oxide (VT') threshold voltages:
= Xo__' Xo where xo x 0'
(1Xo!
= gate oxide thickness = thickness of spurious M O S T oxide ~MS = gate metal-semiconductor work function difference 9'MS = work function difference of spurious MOST 9B = potential difference between real and intrinsic fermi-levels. This expression is obtained by applying Gauss' Law to both oxides, assuming the surface states and oxide charge induce the same amount of charge in the semiconductor and metal. Some difficulty is experienced in defining the
334
W. E C C L E S T O N and M. PEPPER
measuring conditions of the spurious M O S T turnon voltage. The transconductance of the spurious M O S T is given by equation (3). In the case of a thick oxide the capacitance will be a factor of 10 below that of a gate, and the aspect ratio in a circuit will be very poorly defined but generally less than unity. This gives a very low, ill-defined gin. In consequence great care must be taken in defining the current level at which the spurious M O S T is measured as a difference of a factor of 10 in current will give a turn-on difference of many volts. The equation (2) gives a value of V'T of 30 V for an oxide ratio of 10, unity aspect ratio, and a threshold voltage of 4.5 V on 8 ~cm n-type silicon. This would appear to be a sufficiently high value to overcome undesirable spurious effects. For a 2 V threshold device made on 100 orientation silicon, however, and for the same basic parameters, the spurious turn-on voltage is 9 V which could be a cause of difficulty. This can be overcome at the expense of packing density, either by including n ÷ diffusions beneath aluminium rails on thick oxide, or by increasing the distance between adjacent diffusions to reduce the aspect ratio and hence gm of the spurious MOST. 6. P U N C H T H R O U G H
As voltage is applied to the drain of a M O S T the depletion region will extend and avalanche will occur when the critical field is reached. The extent
of the depletion region at avalanche depends on the impurity concentration of the bulk. When the depletion region extends to the source before avalanche, "punch through" will take place. The situation is depicted for a p-channel M O S T in Fig. 6. The field between the source and drain will lower the potential barrier for holes at A. Holes will then be injected into the high field region at B. They may appear there in sufficient numbers to reduce the effect of the applied field on A and thereby reduce any further lowering of the barrier at A. Under these circumstances the current from the source to the drain will be space charge limited, as in MOS devices the density of acceptors and donors in the channel region is low. The current-voltage relationship at punch through is expected to be of the form IDeA VD ~
where AVD is the excess voltage over the punchthrough value. (A simple treatment of this condition is given by Jonscher. (26)) The method of calculating the relationship between punch-through voltage, channel length and bulk impurity concentration depends largely on the form of the diffusion. To determine whether the one-sided step junction or the linear graded junction applies, a "rule of thumb" method has been described by Grove. <6) The diffusion length is (2~/Dt), where D is the diffusion coefficient of the impurity at the temperature of drive-in, and t is
Drain CB.
Source
EF. . . .
FIG. 6. D i a g r a m m a t i c r e p r e s e n t a t i o n of t he p u n c h - t h r o u g h condition.
MODES OF FAILURE OF MOS DEVICES
335
or "roll on". The reverse breakdown voltages of planar diodes increase with increase in reverse voltage. Typically for 8 ~ c m n-type silicon an initial avalanche voltage of 40 V will increase to 50V on increasing the applied voltage. The avalanche characteristic is initially sharp, becoming rounded after "walk-out". On removing the voltage across the diode the breakdown voltage remains at the final high value. Removal of the passivating oxide from an unstressed junction removes also the walk-out, the measured value under these conditions being nearer to the "walkedwBI I+1 ~ l + out" value. Clearly the instability is associated qCB with the presence of the passivating oxide. Increase where CB is the concentration of donors or aceep- of avalanche voltage would be expected from either tors and ~B1 and ~B2 are the potential differences ionic movement across the junction or phosphorus between real and intrinsic Fermi levels in the glass polarization. The latter does not, however, explain the presence of the effect in the absence of diffused junction and bulk silicon respectively. phosphorus stabilization. At temperatures of 77°K Under conditions of punch through: the effect occurs at a similar speed to that at room (a Sq CB] temperature and this is incompatible with the 2KKo ] = Vv (4) observed temperature dependence of the relaxation where a is the channel length and Vv is the punch times of ions. Ionic conduction on top of the oxides can be discounted for this reason, and because the through voltage. We have neglected [ ~ g l [ + [ ~?B2[ as this must be less than the energy gap of walk-out characteristic is still present in the presilicon (1.1 V) and for most practical purposes sence of an aluminium guard-ring on the oxide will be significantly less than Vv. a in this equation above the diffusion perimeter. The effect has been noted (~7, ~8~on n÷p junctions is not the "drawn" spacing of the source and drain but that less the sideways spread of the diffusions. and p+n. The walk-out on the p+n junctions For 8 ~cm silicon a 10 ~m true channel length (p-channel devices) is at least an order of magniwill give a punch-through voltage of 65 V but for tude greater than on n÷p. A possible explanation 3 ~m we obtain a value of 5 V. This punch-through of this effect has been given by Hara et al. c2s~ is the fundamental limit on the source drain The avalanching junction contains carriers of both spacing. The resistivity of the silicon can be types and these will be present with sufficient decreased to increase the punch-through voltage, energy just inside the silicon surface to enter the but this will increase junction capacitance, decreas- oxide, by negotiating the electron affinity of the ing circuit speed and increasing the device thresh- semiconductor. It is not clear whether the energy hold voltage. The punch-through voltage is very levels into which the carriers enter are always dependent on the voltage applied to the gate. This present or are in some way created by the applied is particularly true for a "pinched-off" channel. fringing field. The effect can be controlled by use Gross distortion of the device characteristics may of a field electrode around the junction perimeter. occur at gate voltages above threshold. When the Some recovery is seen if the device is heated for high voltage drain characteristics is apparently long periods of time. limited by avalanche, punch through may still The instability is not normally classed as a mode increase leakage currents between source and drain of failure but because it involves depletion layer for lower drain voltages. widening along the channel it must be allowed for in calculating source drain spacings. Hara et al. 7. UNSTABLE DIODE AVALANCHE VOLTAGE indicate a 30 per cent change in channel length of This effect is present on MOS devices and is a 4 izm device, which becomes only a 1 per cent known by a variety of names, such as "walk-out" change in a 200 ~m device. The amount of the time of the drive-in. If the width of the depletion region is greater than the diffusion length then the one-sided step junction approximation applies. If the width of the depletion region is less than the diffusion length the linear graded junction approximation is used. For most practical MOS structures the one-sided step junction represents a very good approximation. From the application of Poisson's equation to this type of impurity profile the width W of a depletion region can be shown to be:
W=/2KKo(I
VD)
336
W. E C C L E S T O N
walkout is, of course, a strong function of the bulk impurity density. On 2f~cm n-type material the walk-out is reduced to a few volts for levels of positive charge in the oxide between 1011 and 101~ e- cm-L 8. OTHER CAUSES OF DIODE LEAKAGE
8.1 Irregular oxide photo-engraving The avalanche voltage both before and after walk-out is a function of the field across the depletion region of the junction. This field can be increased by a junction curvature either normal or parallel to the surface of the silicon. Breakdown at curvature normal to the surface will occur in planar technology owing to the cylindrical nature of the diffusion profile. Curvature in the plane of the surface can be caused by sharp corners produced intentionally or accidentally on the oxide windows. 8.2 Silicon defects Defects within the area of the depletion region will cause high leakage in the reverse characteristics. This will only occur when the defect is situated within the depleted region, so that leakage currents at low reverse voltages may be normal36) A large amount of work has been carried out on silicon defects, most of which is applicable to M O S devices. These defects can be process induced or can be present in the initial material.
and M. P E P P E R
To reduce process induced defects the following general rules apply: (a) Avoid mechanical damage, particularly to the edge of the slice. (b) Wherever possible keep processing temperatures below 1000°C. (c) Wherever possible lie slices flat during high temperature operations. Because defects are likely to be grouped around the edge of the slices the loss of chips from this area will be greater than that at the centre. (29-31~ For a given average density of defects, therefore, the yield in the centre will be higher than for spatially random defects. The relationship between yield of good chips and chip area will be of the form which gives greater yields than expected for a logarithmic distribution. 8.3 Field induced junctions Care must be taken in terminating the metallization of source and drain. This can act as a relief electrode and produce an extension of the true diffused junction beneath the metal as shown in Fig. 7. A new junction is produced at the edge of the metal which may have a lower breakdown voltage than that of the true diffused junction. (6) Increasing the voltage across the junction causes the conducting channel to pinch-off after the initial avalanche occurs. The field induced junctions Light
FIG. 7. The condition at a source or drain likely to lead to field induced junctions and spurious diode leakage.
FIc. 8. Incomplete coverage of an oxide step due to the position of the filament used for evaporation. T h e width of the aluminium stripe is 12 ~.
facing page 336
Fie;. 9. T h e effect of e t c h i n g a n a l u m i n i u m s t r i p e on top of a c r e v i c e i n a d e p o s i t e d o x i d e o n a first l a y e r s t r i p e of a l u m i n i u m .
M O D E S OF F A I L U R E OF MOS D E V I C E S may be light sensitive and care must be taken to measure them under dark conditions in assessing their importance. They are, of course, a major source of difficulty in self-scanned silicon diode photo-arrays where such a relief electrode may be used to reduce leakage currents and thereby improve sensitivity. This is only possible at voltages below the breakdown voltage of the field induced junction. At quite a low voltage the field induced junction will avalanche and pinch-off. At higher voltages much higher leakages will be present, and any benefit from the relief electrode will be negative, especially as in the case of self-scanned arrays where light is necessarily present. 9. INADEQUATE CONTACTS Low resistance contacts between the metal and diffusions is a normal requirement of MOS circuits. This is achieved by photo-engraving oxide regrown on the diffusion before metallization. The stages are: (a) Apply resist, expose and develop. (b) Etch regrown oxide. (c) Remove resist by using an oxidizing medium. (d) Evaporate metal. (e) Photo-engrave metal. (f) Anneal for 10-30 rain at 400-500°C in inert ambient. The etching of the regrown oxide can cause problems on boron diffused regions. During deposition of the boron a silicon-boron phase is produced in the windows. Upon oxidation this produces a region in the oxide of low etch rate next to the silicon. In removing this region, gross undercutting of the remaining oxide will occur, especially when this contains phosphorus for stability purposes. Ellipsometer investigations indicate that this low etch rate oxide is within 100 A of the silicon and can be removed by successive treatment of the slice in hydrofluoric acid, followed by boiling nitric acid, followed by hydrofluoric acid. (The hydrofluoric acid must, of course, be diluted to prevent removal of thicker oxides on the remainder of the circuit.) When the slow etching phase has been removed, the photoresist has still to be removed. This is carried out using an oxidizing medium, and will cause some oxide to be grown in the contact hole. This may only be 20 A in thickness, but is sufficient to cause contact resistance between the metal
337
and the silicon. For this reason it is necessary to heat treat the silicon slice after metaUization. This is normally carried out at 400-500°C. The higher temperature will give more effective contacts and will more effectively annihilate surface states, but will also be a source of oxide defects. ~21~A compromise must therefore be made between the three effects. Reduction of the thin oxide film present after resist removal is obviously advantageous. Care must be taken to ensure effective resist removal, as this is a cause of breaks in aluminium rails on the finished circuits. Contact resistance may distort the M O S T characteristics depending on the electrical conduction processes in the thin oxide film. Smaller contact resistances will produce substrate bias effects, thereby shifting the threshold voltage of the device to more negative values. An effect more important than the change in the value of VT is likely to be that of non-reproducible contact resistances on spatial variations of this parameter. 10. IVIETALLIZATION DEFECTS
As stated previously, failure of a chip to operate may be attributed to open circuit aluminium rails. This can be caused by electromigration 182~ or breaks due to resist left behind after contact photoengraving, or breaks over oxide steps. The latter is particularly severe in MOS devices because of the high ratio required between threshold voltage and the turn-on voltage of the spurious MOST. The extent of aluminium breaks on steps depends not only on the thickness of the metal but also on evaporation geometry. Figure 8 shows a step on an MOS chip facing away from the source of metal. Effective coverage can be achieved by rotating the slice during metallization. The problem of metallizing oxide steps can be particularly severe on processes using deposited dielectrics, e.g. silicon gate, refractory metal gate and multilayer technology. A stated advantage of these processes is to pass metal over active devices, thereby increasing packing density. Deposited dielectric separates the two layers of metallization. Whether the dielectric is produced by chemical deposition or by r.f. sputtering, a crevice is produced. On application of the second metal and photoengraving the result is shown in Fig. 9. This is a likely source of loss of yield or of failure during the life of the device.
W. E C C L E S T O N
338
I I . CONCLUSION Descriptions of the physical basis of the most p r o m i n e n t modes of failure of M O S devices have been described. T h e means of distinguishing between the various causes of failure are discussed. References are given to more comprehensive treatm e n t of p h e n o m e n a . A diagnostic table is presented also which optimizes the sequence of m e a s u r e m e n t for labelling failure modes and describes also the various symptoms. T h e information required b y this table can be added to b y optical and s c a n n i n g electron microscopy as well as b y temperature bias stressing, and the means of interpreting the latter are described in the text.
Acknowledgements--The authors would like to thank Mr. P. C. Newman and Mr. K. J. S. Cave of Allen Clark Research Centre for critically reading the manuscript. We would also like to thank the directors of the Plessey Company for permission to publish this review.
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