Parameters extraction of hafnium based gate oxide capacitors

Microelectronics Reliability 47 (2007) 729–732 www.elsevier.com/locate/microrel

Parameters extraction of hafnium based gate oxide capacitors T. Nguyen a

a,*

, C. Busseret a, L. Militaru a, A. Poncet a, D. Aime´

a,b

, N. Baboux a, C. Plossu

a

Laboratoire de Physique de la Matie`re, UMR CNRS 5511, INSA – Lyon, Baˆt B. Pascal, BP 69, 69621 Villeurbanne, France b STMicroelectronics, 850, Rue Jean Monnet, 38926 Crolles Cedex, France Available online 8 March 2007

Abstract From quantum simulations of both capacitance and current measurements, the main physical parameters (dielectric thickness and permittivity, doping levels) of hafnium based (HfSiOx and HfO2) gate oxide capacitors have been extracted. Three kinds of gates (n+-polysilicon, totally silicided (TOSI) NiSi and metal TiN gates) have been studied. In the case of thick (EOT between 11.1 and 12.3 nm) HfSiOx gate oxides or thin (EOT inferior to 2 nm) HfO2 stacks with n+-polysilicon or TiN gates, a good agreement between simulations and experimental data is obtained. Electron tunneling currents are prevalent in these stacks except for the specific case of TiN/HfO2 stacks in p-substrate accumulation mode. In this case, electron and hole tunneling transparencies become of the same order of magnitude. Hole transport contribution can no more be neglected and should be taken into account in simulations.  2007 Elsevier Ltd. All rights reserved.

1. Introduction According to Moore’s law, the gate oxide thickness must be reduced in order to maintain a correct scaling of MOS transistors dimensions. Due to the occurrence of high level direct tunneling currents, we are approaching the limits in reducing silicon dioxide (SiO2) gate thickness. Future CMOS technology nodes will require the introduction of alternative high-k dielectrics such as hafnium based oxides (HfO2, HfSiOx, etc.) which appear at present as the most serious candidate. Another technical challenge is to introduce metal gates to avoid polysilicon depletion phenomenon. One of the main technological problem encountered in the elaboration of high-k gate dielectric is the formation of interfacial SiO2 which leads to an increase of the equivalent oxide thickness (EOT). A precise extraction of the high-k layer thickness and permittivity and of the thickness of the interfacial SiO2 layer thickness is required for process optimization and gate current simulations. In this paper we present a study of HfO2 and HfSiOx gate oxide capacitors with three kinds of gate: metal TiN, totally sili*

Corresponding author. Tel.: +33 04 72 43 70 36; fax: +33 04 72 43 60

82. E-mail address: [email protected] (T. Nguyen). 0026-2714/$ - see front matter  2007 Elsevier Ltd. All rights reserved. doi:10.1016/j.microrel.2007.01.061

cided NiSi (TOSI) and n+-polysilicon. Considering a dual gate oxide layer (HfO2/SiO2 and HfSiOx/SiO2), the physical parameters of high-k stacks have been extracted from quantum simulations of experimental capacitance–voltage (C–V) and current–voltage (I–V). 2. Samples and experimental procedure The characteristics of the different high-k stacks and reference SiO2 devices are reported in Tables 1 and 2. The first high-k stacks (Table 1) consist of an HfSiOx layer deposited on SiO2. An O2 post-deposition anneal at 800 C was performed and a phosphorus-implanted polysilicon layer was deposited. Some samples were then totally siliciced with a two-step process (Nickel deposition then anneal) to form TOSI NiSi arsenic doped gates [1]. The second high-k stacks (Table 2) consist of HfO2 with an interfacial SiO2 oxide layer. A N2 post-deposition anneal at 600 C was performed in the case of TiN electrode gate and at 800 C for polysilicon electrode gate. Two reference samples with SiO2 gate oxide were elaborated. All the samples have a p-type Si substrate. High frequency (10 kHz) and quasi-static capacitance– voltage C–V measurements were performed. A homemade 1 D quantum C–V simulator [2] was used to adjust

730

T. Nguyen et al. / Microelectronics Reliability 47 (2007) 729–732

Table 1 HfSiOx/SiO2 samples Gate +

n -PolySi TOSI (As)

HfSiOx

SiO2

EOT

4 nm 4 nm

11 nm 9.8 nm

12.3 nm 11.1 nm

EOT is the equivalent SiO2 electrical thickness.

Table 2 HfO2/SiO2 samples Gate

HfO2

SiO2

EOT

4 nm

1.95 nm 1.2 nm

1.95 nm 1.5 nm

2 nm 3 nm

2 nm 1.1 nm 1.05 nm

2 nm 1.5 nm 1.6 nm

n+-PolySi TiN

Fig. 1. C–V measurements and simulations on n+-PolySi /HfSiOx/SiO2/ p-type Si substrate device.

EOT is the equivalent SiO2 electrical thickness.

simulated C–V curves to experimental ones. In the case of polysilicon gates, both electrodes were treated according to the same quantum model. The following physical parameters were extracted: dielectric thicknesses (thigh-k, and tSiO2), high-k layer permittivity (ehigh-k), substrate (Nsub) and gate (Ngate) doping levels, interface state density (Dit). Using these parameters, the conduction tunneling current density was then calculated considering a dual layer model [3]. The calculation of the dielectric barrier electron tunnel transparency was based on a transfer matrix [4] formalism in which the solutions of Schro¨dinger equation are the Airy functions. The tunneling current is given by (1): X J¼ nðEi Þf ðEi ÞT ðEi Þ ð1Þ i

where Ei is the eigenenergy, n(Ei) the states density, f(Ei) the escape frequency and T(Ei) the barrier transparency. Experimental I–V current–voltage curves were finally compared to calculated ones. 3. Results and discussion 3.1. HfSiOx devices High frequency (10 kHz) and quasi-static C–V measurements are reported in Fig. 1 in the case of HfSiOx and polysilicon gate devices. From quantum C–V simulation (Fig. 1), the following parameters have been extracted: eHfSiOx = 15, thigh-k = 4 nm, tSiO2 = 11 nm, Ngate = 4 · 1019 cm3, Nsub = 3.5 · 1017 cm3. The experimental I–V characteristic and the tunneling current simulation for the same device are displayed in Fig. 2. The potential barrier heights at the different interfaces are: /b PolySi/HfSiOx = 2 eV, /b Si/SiO2 = 3.1 eV. The following electron effective masses in HfSiOx and SiO2 have been used for simulations: mHfSiOx = 0.18m0, mSiO2 = 0.5m0 where m0 is the free electron mass. Good agreement is observed between experimental data and tunneling current simulation in the FN injection regime.

Fig. 2. I–V measurements and simulations on n+-PolySi/ HfSiOx/SiO2/ p-type Si substrate device.

Fully silicided (NiSi) gate capacitors have been next studied as described previously. The following parameters were extracted: eHfSiOx = 12, thigh-k = 4 nm, tSiO2 = 9.8 nm, Nsub = 3.5 · 1017 cm3. We can observe that HfSiOx permittivity in TOSI samples is lower than in n+-PolySi samples. This observation is not at present physically explained. Fig. 3 shows the measured and simulated current on TOSI/HfSiOx/SiO2/Si device. Using a potential barrier height /b TOSI/HfSiOx = 2.15 eV (/b As-TOSI = 4.2 eV), we obtained a good concordance between experimental and simulated curves. The current level for the device with TOSI gate (Fig. 3) is higher than for device

Fig. 3. I–V measurements and simulations on TOSI/HfSiOx/SiO2/p-type Si substrate device.

T. Nguyen et al. / Microelectronics Reliability 47 (2007) 729–732

Fig. 4. C–V measurements and simulations on TiN/HfO2/SiO2/p-type Si substrate device.

with a polysilicon gate (Fig. 2), that can be explained by the higher thickness of SiO2 interfacial layer for n-poly device than for TOSI device. 3.2. HfO2 devices

731

As can be seen in Fig. 5 in the case of n+-PolySi gate samples, a very good agreement between experimental data and simulations has been obtained for both gate polarities. The potential barrier heights at the different interfaces are: /b PolySi/HfO2 = 1.7 eV, /b PolySi/SiO2 = 3.1 eV [7]. The gate current Jg is dominated by the electron current JCBe injected from the cathode conduction band (from the substrate in inversion mode at Vg > 0 and from the polySi gate in substrate accumulation mode at Vg < 0). In substrate accumulation mode, the electron gate current JCBe is dominating, compared to hole injection from the substrate due to a much lower potential barrier height for electrons (/b(e)PolySi/HfO2 = 1.7 eV, /b(h+)Si/SiO2 = 4.5 eV). Once the model has been validated for polysilicon gate, we have studied TiN gate behavior. Experimental and simulated current data in inversion mode (Vg > 0 V) are reported in Fig. 6, for the SiO2 reference sample and for various thicknesses of HfO2 oxides. One can observe that simulation and experimental curves are in good agreement in the high field domain. The gate current Jg is dominated by electron injection from the inversion layer in the substrate. Results in accumulation mode (Vg < 0 V) are presented in Fig. 7. One can observe that a good simulation can be achieved only in the case of the TiN/SiO2 reference sample

Very thin HfO2 gate oxides (Table 2) with EOT below 2 nm have been also studied. Experimental and quantum simulated C–V curves are represented in Fig. 4 for 3 nm HfO2 and 1 nm SiO2 (EOT = 1.7 nm) with a TiN electrode. Extracted values from the capacitance simulation are: eHfO2 = 21, tHfO2 = 3 nm, tSiO2 = 1.05 nm, Nsub = 2 · 1017 cm3 in good agreement with nominal values. It must be noticed that we have to consider the presence of interface states with density Dit = 3 · 1011 eV1 cm2 to fit the experimental curve at low electric fields (0.5 V < Vg < 0.5 V). This Dit value is in good agreement with that previously obtained by charge-pumping measurements on the same devices [5]. Conduction currents have been next studied in the case of n+-PolySi and TiN gates. In order to clarify conduction mechanisms, measurements and simulations have been performed on both HfO2/SiO2 and SiO2 reference samples. The electron effective mass in HfO2 is mHfO2 = 0.18m0 [6].

Fig. 6. Measured and simulated gate tunneling current for SiO2 and HfO2/SiO2 oxides with TiN gate in substrate inversion mode (Vg > 0).

Fig. 5. Measured and simulated gate tunneling current for SiO2 and HfO2/SiO2 oxides with n+-PolySi gate. For HfO2 samples, Garros’ experimental data [7] have been reported.

Fig. 7. Measured and simulated gate tunneling current for SiO2 and HfO2/SiO2 oxides with TiN gate in substrate accumulation mode (Vg < 0). For SiO2 samples, Garros’ experimental data [7] have been reported.

732

T. Nguyen et al. / Microelectronics Reliability 47 (2007) 729–732

in the high field domain. In this case, the gate current Jg is mainly due to electron injection from the gate. Hole injection current JVBh from the substrate is negligible compared to electron current JCBe (/b(e)TiN/SiO2 = 3.4 eV, /b(h+)Si/SiO2 = 4.5 eV) [8]. For TiN/HfO2 devices, one can observe in Fig. 7 that the simulated curves are lower than the experimental curves by more than one decade in the high field domain. In this case the electron barrier height at the TiN/HfO2 interface is higher (/b(e)TiN/HfO2 = 2.2 eV) compared to that at the PolySi/HfO2 interface (/b(e)PolySi/HfO2 = 1.7 eV). The electron tunneling transparency decreases so that the hole transparency becomes of the same order of magnitude. Only the electron current being taken into account in the modeling, it will be necessary to consider the holes current which is not negligible anymore in this case (TiN/HfO2). This would justify that the current obtained by simulation is lower than the experimental current. These results are in agreement with the conclusions of Garros [7]. One can also observe that experimental currents at low electric field are higher than simulated ones. This discrepancy is due to tunneling currents via interface states which are not considered in this model. 4. Conclusion We have shown that quantum simulations of capacitance and current measurements allow the determination of double gate dielectric layer constants, permittivity and thickness. For thin HfO2 oxides with PolySi gate, we have

a very good agreement between experimental data and simulation for both gate polarities when we consider only electron currents. In the specific case of TiN metal gate, it is mandatory to take into account both electrons and holes transport contributions. References [1] Aime D, Froment B, Cacho F, Carron V, Descombes S, Morand Y, et al. Work function tuning through dopant scanning and related effects in Ni fully silicided gate for sub-45 nm nodes CMOS. In: Proceedings of international electron devices meeting, IEDM, 2004. p. 87–90. [2] Busseret C, Baboux N, Plossu C, Poncet A. Ultra fast full quantum capacitance–voltage calculations of mos capacitors. In: Proceedings of ULIS – 7th European workshop on ultimate integration of silicon – Grenoble, ULIS, 2006. p. 169–72. [3] Govoreanu B, Blomme P, Rosmeulen M, Houdt JV, De Meyer K. A model for tunneling current in multi-layer tunnel dielectrics. SolidState Electron 2003;47(6):1045–53. [4] Wayne W Luim, Fukuma M. Exact solution of the Schrodinger equation across an arbitrary one-dimensional piecewise-linear potential barrier. J Appl Phys 1986;60(5):1555–9. [5] Militaru L, Weber O, Muller M, Ducroquet F, Dusciac D, Plossu C, et al. Study of electrically active defects in high mobility HfO2 MOSFETs. In: Proceedings of the 34th European solid-state device research conference, ESSDERC, 2004. p. 181–4. [6] Hou YT, Li MF, Yu HY, Jin Y, Kwong DL. Quantum tunneling and scalability of HfO2 and HfAlO gate stacks. In: Proceedings of international electron devices meeting, IEDM, 2002. p. 731–4. [7] Garros X. Universite´ de Province – Aix – Marseille 1, Ph.D. thesis; 2004. ISBN 2004AIX11067. [8] Westlinder J, Schram T, Pantisano L, Cartier E, Kerber A, Lujan GS, et al. On the thermal stability of atomic layer deposited TiN as gate electrode in MOS devices. IEEE Electron Dev Lett 2003;24(9):550–2.