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Reliability and gate conduction variability of HfO2-based MOS devices: A combined nanoscale and device level study
Microelectronic Engineering 88 (2011) 1334–1337
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Reliability and gate conduction variability of HfO2-based MOS devices: A combined nanoscale and device level study A. Bayerl a,⇑, M. Lanza a, M. Porti a, F. Campabadal b, M. Nafría a, X. Aymerich a, G. Benstetter c a
Dept. Eng. Electrònica, Universitat Autònoma de Barcelona, 08193 Bellaterra, Barcelona, Spain Institut de Microelectrònica de Barcelona, IMB-CNM, CSIC, 08193 Bellaterra, Barcelona, Spain c Dept. Electrical Engineering, Deggendorf University of Applied Sciences, 94469 Deggendorf, Germany b
a r t i c l e
i n f o
Article history: Available online 30 March 2011 Keywords: MOS devices Atomic Force Microscopy Reliability Variability High-k dielectric High-k crystallization
a b s t r a c t The electrical properties and reliability of MOS devices based on high-k dielectrics can be affected when the gate stack is subjected to an annealing process, which can lead to the polycrystallization of the high-k layer. In this work, a Conductive Atomic Force Microscope (C-AFM) has been used to study the nanoscale electrical conduction and reliability of amorphous and polycrystalline HfO2 based gate stacks. The link between the nanoscale properties and the reliability and gate conduction variability of fully processed MOS devices has also been investigated. Ó 2011 Elsevier B.V. All rights reserved.
1. Introduction Intrinsic process variability and aging mechanisms strongly affect the device performance and reliability, especially in ultrascaled MOS devices [1]. Electrical characteristics of such devices may show large device-to-device variability, which is ultimately associated with the discrete nature of matter and charge. Several variability sources, such as random dopant distribution, among others, have been identified [1]. The homogeneity of the morphological and electrical properties of the high-k gate stack may also be expected to affect the variability of the electrical properties of scaled devices. However, few reports have addressed this topic since standard electrical characterization techniques only provide average information of the complete gate area of fully processed devices [2,3]. On the other hand, during the operation of the device within the circuit, aging mechanisms of the gate dielectric also appear, as defect generation and the dielectric breakdown (BD), which will modify the electrical characteristics of devices. The device aging can introduce large and time-dependent shifts in the parametric figures of devices [4] and circuits [5] and reduce their reliability. To have a more detailed insight on the origin of the variability sources, measurement techniques with a high local resolution are needed in order to study processes at a smaller scale. Scanning probe microscopy and, in particular, Conductive Atomic Force Microscopy (C-AFM), can be used to characterize dielectrics at ⇑ Corresponding author. Tel.: +34 935812517; fax: +34 935812600. E-mail addresses: [email protected], [email protected] (A. Bayerl). 0167-9317/$ - see front matter Ó 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2011.03.122
highly increased resolution [6–9]. In this case, the conductive tip of the C-AFM and the bare gate dielectric stack forms a MOS capacitor with an area of few hundreds of nm2. By applying a voltage, current flows through the structure, which allows evaluating the dielectric electrical properties with nanometer resolution. This technique has been used, for example, to evaluate the impact of some manufacturing processes (like high temperature annealing, which can lead to the gate stack polycrystallization) on the nanoscale electrical properties of high-k dielectrics [10]. However, few works have been devoted to investigate the link between the nanoscale electrical properties and the variability and reliability observed at device level, i.e., on fully processed MOS devices. In this work, a C-AFM and standard wafer level characterization techniques are used in combination to study how the polycrystallization (after a thermal annealing) of the high-k dielectric of MOS capacitors affects their morphological and electrical properties at the nanoscale and the impact of such nanoscale properties on the reliability and variability of the global gate electrical characteristics of fully processed MOS devices. The impact of an electrical stress on the nanoscale and device level properties of amorphous and a polycrystalline structure is also investigated. 2. Experimental The investigated samples consist in MOS capacitors (3 3 lm2) with an Al gate electrode and a HfO2 film as gate dielectric deposited at 225 °C by atomic layer deposition (ALD) on a n-type Si substrate. The oxide thickness, measured by ellipsometry on as deposited dielectrics, was 3.6 nm. Some of the structures were
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annealed at high temperature (TA = 800 °C) to get a polycrystalline high-k layer while others were kept amorphous (annealing at TA = 350 °C). The annealing was performed before gate deposition in an inert nitrogen ambient during 30 min. For both TA, fresh (non-stressed) and stressed (by a Constant Current Stress, CCS, at 5 nA during 300 s or until BD) capacitors were analyzed at the nanoscale and at device level to evaluate the impact of an electrical stress. The variability of the global electrical properties of fully processed MOS devices was analyzed from the measurement of their IG–VG curves with a semiconductor parameter analyzer. The nanoscale electrical properties of some of those structures were investigated with C-AFM (in dry nitrogen ambient and using Pt–Ir coated silicon tips) after the Aluminum gate was removed with a highly selective wet etching. With the C-AFM, current and topography maps were obtained when applying a constant voltage between the tip and the sample during the scan. I–V curves measured at different oxide locations were also registered. Device level and nanoscale measurements were performed on structures coming from the same wafer and the same die, to avoid waferto-wafer and die-to-die variability. 3. Results and discussion
amorphous
polycrystalline
rms:0.11nm
rms:0.18nm
rms:0.15nm
rms:0.37nm
after stress
before stress
To begin with, the impact of the polycrystallization on the nanoscale morphological properties of HfO2 gate stacks was investigated with C-AFM after removing the gate contact. As an example, Fig. 1 shows topographical images of amorphous (a and c) and polycrystalline (b and d) HfO2 layers before (a and b) and after (c and d) being electrically stressed. Before the stress, the polycrystalline sample (Fig. 1b) shows a granular structure (leading to a larger rms value of the surface), which is not observed in Fig. 1a (amorphous). This granularity has been attributed to the presence of randomly orientated nanocrystals separated by grain boundaries (GBs) [10–12], which correspond to the depressed regions in the image. The larger topographical inhomogeneity observed after polycrystallization suggests larger local thickness (tox) fluctuations
within the polycrystalline structures. After the stress (Fig. 1c and d, obtained on amorphous and polycrystalline gate stacks, respectively), the topographical inhomogeneity increases with respect to unstressed samples (Fig. 1a and b). This effect can be probably related to artifacts of the measuring technique associated to charge trapping in the defects generated during the CCS [13]: the trapping/detrapping of elementary charges in/from the defects created during the stress can lead to additional electrostatic interactions between the C-AFM tip and the gate stack. These interactions are interpreted by the C-AFM setup as topographical fluctuations which, actually, are not real. Since Fig. 1 shows, after the stress, a larger increase of the rms value on polycrystalline samples, these results suggest that the spatial distribution of the defects is more inhomogeneous in those samples compared to those that are amorphous. The impact of an electrical stresses on the nanoscale electrical conduction of amorphous and polycrystalline gate stacks has been investigated from the measurement of current images and I–V curves with the C-AFM. Fig. 2 shows, as an example, current images measured by applying the minimum voltage that forces a current just above the noise level on amorphous (a and c) and polycrystalline (b and d) samples before (a and b) and after (c and d) the electrical stress. Note that the current rms value follows the same tendency as surface roughness: polycrystalline samples are more inhomogeneous and the stress has a larger impact on such structures, that is, larger changes in the rms values are measured after the stress. These results are further supported by the measured I–V curves. Fig. 3 shows two sets of I–V characteristics obtained with C-AFM on amorphous (a) and polycrystalline (b) samples, before and after the stress. Table 1 (1st and 2nd rows) indicates the mean value and standard deviation of the gate voltage necessary to measure a current of 10 pA (VI), obtained from the I–V curves in Fig. 3. Note that, the smaller VI, the larger the conductivity of the stack. Fig. 3 and Table 1 show that after the stress, the average electrical conduction is reduced (shift onto larger VI values), probably due to charge trapping in the defects generated during the
2nm
0
amorphous
polycrystalline
rms:0.27pA
rms:0.36pA
rms:0.36pA
rms:4.45pA
after stress
before stress
Fig. 1. Topographical images obtained on the (a and c) amorphous and (b and d) polycrystalline gate stack, before (a and b) an after (c and d) the electrical stress. The surface roughness is also included in the figure.
2pA
0
Fig. 2. Current images obtained on the (a and c) amorphous and (b and d) polycrystalline gate stack, before (a and b) and after (c and d) the electrical stress. The rms value before and after the electrical stress is also included.
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Fig. 3. I–V curves obtained with CAFM, before and after the stress, on the (a) amorphous and (b), polycrystalline annealed samples. The area of the MOS structure under analysis is determined by the tip-sample contact region, which is of the order of few hundreds of nm2.
Nanoscalr 10 pA
hVIi (V)
r (mV) Device level 1 nA
hVIi (V)
r (mV)
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Polycrystalline
Fresh
Stressed
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Stressed
3.74 129
4.09 154
5.72 247
6.61 343
0.86 4.2
0.87 4.9
0.25 110
– –
CCS. Moreover, again, the dispersion increases and becomes much larger after the stress in polycrystalline samples. This effect could be related to the different electrical properties between GBs and nanocrystals in polycrystalline structures. GBs, probably with an initial excess of some kind of native defects (generated during polycrystallization), could be even more affected by the electrical stress, leading to larger fluctuations of the electrical conduction after the stress, detected as an increase of the conductivity deviation (Table 1 and Fig. 3). Therefore, the results obtained with CAFM show that the polycrystallization of the high-k layer is an important source of nanoscale electrical variability, which further increases after an electrical stress. But, how does this nanoscale variability affect the performance of MOS devices? In this section, in an effort to evaluate the impact of the previously analyzed nanoscale variability sources and the
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effect of an electrical stress on the global electrical properties and reliability of MOS capacitors, some of the fully-processed devices have been investigated with standard characterization techniques. In particular, the gate conduction and the electric field at breakdown (EBD) has been evaluated from the I–V characteristics measured before and after the electrical stress. Fig. 4 shows some I–V characteristics measured on the amorphous (a) and polycrystalline (b) Al-gated capacitors, before (squares) and after (triangles) the stress. The mean value and dispersion of the onset voltage, VI, necessary to detect a current of 1 nA has been used to quantify oxide conductivity (Table 1, rows 3 and 4). At device level (after the stress), in the polycrystalline samples, no data is added since all capacitors were broken down during the stress and post-BD currents are larger than 1 nA (at very low voltages, see Fig. 4b). First, it must be noted that a direct comparison between the currents in Fig. 4a (capacitors data) and Fig. 3a (CAFM data) is not meaningful, because experimental factors (such as changes on the tip conductivity, contact area, small variations of the oxide thickness or different gate electrodes) can affect the value of the measured current. However, since we are only interested in relative variations of conductivity, the experimental related differences do not change the conclusions of the work. In Fig. 4a (amorphous), those capacitors that do not break down during the CCS show a reduction of the electrical conduction and an increment of the dispersion (Table 1) compared to fresh structures. Both effects could be related to the random generation of defects during the stress, which could trap charge (shift onto higher voltages) and modify locally the gate stack conductivity (larger fluctuations). In (b), (polycrystalline samples), before the stress,
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cumulative failure ln(-ln(1-F))
Table 1 Mean value and deviation of the gate voltage (VI) necessary to measure a current of 10 pA (nanoscale measurements) and 1 nA (device level measurements), obtained from the I–V curves in Figs. 3 and 4, respectively. At device level, in the polycrystalline sample, no data is added since all capacitors were broken down during the stress and post-BD currents are larger than 1 nA for very low voltages.
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Fig. 4. I–V curves obtained on Al-gated structures (3 3 lm2), before (squares) and after (triangles) the stress, on the (a) amorphous and (b) polycrystalline samples. (c) Shows the EBD Weibull distribution of the different samples when subjected to RVS.
A. Bayerl et al. / Microelectronic Engineering 88 (2011) 1334–1337
the gate conduction is larger and shows a higher dispersion than that in amorphous gate dielectrics (Fig. 4a), probably due to presence of grain boundaries, which have been found to be leakier [10]. Moreover, all of the capacitors broke down during the CCS. Actually, Fig. 4c shows the EBD Weibull distributions of the analyzed structures when subjected to ramped voltage stress (RVS). The results show smaller values and larger dispersions of EBD after polycrystallization. Therefore, these results indicate that polycrystalization of the high-k layer not only affects the variability of the electrical properties of MOS devices, but also their reliability. 4. Conclusions In this work, the relation between the nanoscale and device level gate conduction variability and reliability of MOS devices based on amorphous and polycrystalline HfO2 gate stacks has been studied. Polycrystallization of high-k dielectrics increases the inhomogeneity of the nanoscale surface morphology, conductivity and trapping properties, which is enhanced after an electrical stress. These nanoscale inhomogeneities are transferred to the global gate electrical properties of fully processed MOS devices. In particular, gate current variability increases much more in polycrystalline samples. Moreover, a reduction of their reliability is also measured. The results show that the larger the initial (before any stress) variability of the gate stacks properties (due to polycrytallization of high-k dielectrics, in this work), the larger the impact of an electrical stress on their nanoscale and device level electrical properties and reliability.
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Acknowledgements This work has been partially supported by the Spanish MICINN (TEC2007-61294, TEC2010-16126 and GICSERV5-NGG120) and the Generalitat de Catalunya (2009SGR-783). References [1] A. Asenov, S. Roy, R.A. Brown, G. Roy, C. Alexander, C. Riddet, C. Millar, B. Cheng, A. Martinez, N. Seoane, D. Reid, M.F. Bukhori, X. Wang, U. Kovac, IEEE Electron Device Meet. Tech. Digest (2008). [2] J. Robertson, Rep. Prog. Phys. 69 (2006) 327–396. [3] R. Degraeve, M. Aoulaiche, B. Kaczer, P. Roussel, T. Kauerauf, S. Sahhaf, G. Groeseneken, Proc. 15th Phys. Failure Anal. Integr. Circuits (IPFA) (2008) 1–6. [4] M. Alam, Microbiol. Reliab. 9 (2008) 1114–1122. [5] W. Hua, M. Miranda, F. Catthoor, W. Dehaene, IEEE Trans. Device Mater. Reliab. 7 (4) (2007) 581–591. [6] Y.L. Wu, S.T. Lin, C.P. Lee, IEEE Trans. Device Mater. Reliab. 8 (2) (2008) 352– 357. [7] P. Fiorenza, W. Polspoel, W. Vandervorst, Appl. Phys. Lett. 88 (22) (2006). Art. No. 222104. [8] M. Lanza, M. Porti, M. Nafría, X. Ayermich, A. Sebastiani, G. Ghidini, A. Vedda, M. Fasoli, IEEE Trans. Device Mater. Reliab. 9 (4) (2009). [9] W. Frammelsberger, G. Benstetter, Appl. Surf. Sci. 252 (6) (2006) 2375–2388. [10] V. Iglesias, M. Porti, M. Nafría, X. Aymerich, P. Dudek, T. Schroeder, G. Bersuker, Appl. Phys. Lett. 97 (26) (2010) 262906. [11] V. Yanev, M. Rommel, M. Lemberger, S. Petersen, B. Amon, T. Erlbacher, A.J. Bauer, H. Ryssel, A. Paskaleva, W. Weinreich, C. Fachmann, J. Heitmann, U. Schroeder, Appl. Phys. Lett. 92 (25) (2008). [12] P. Gusev, C. Cabral Jr., M. Copel, Microelectron. Eng. 69 (2–4) (2003) 145–151. [13] M. Porti, M. Nafría, M.C. Blüm, X. Aymerich, Appl. Phys. Lett. 81 (19) (2002) 3615–3617.
Contents lists available at ScienceDirect
Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee
Reliability and gate conduction variability of HfO2-based MOS devices: A combined nanoscale and device level study A. Bayerl a,⇑, M. Lanza a, M. Porti a, F. Campabadal b, M. Nafría a, X. Aymerich a, G. Benstetter c a
Dept. Eng. Electrònica, Universitat Autònoma de Barcelona, 08193 Bellaterra, Barcelona, Spain Institut de Microelectrònica de Barcelona, IMB-CNM, CSIC, 08193 Bellaterra, Barcelona, Spain c Dept. Electrical Engineering, Deggendorf University of Applied Sciences, 94469 Deggendorf, Germany b
a r t i c l e
i n f o
Article history: Available online 30 March 2011 Keywords: MOS devices Atomic Force Microscopy Reliability Variability High-k dielectric High-k crystallization
a b s t r a c t The electrical properties and reliability of MOS devices based on high-k dielectrics can be affected when the gate stack is subjected to an annealing process, which can lead to the polycrystallization of the high-k layer. In this work, a Conductive Atomic Force Microscope (C-AFM) has been used to study the nanoscale electrical conduction and reliability of amorphous and polycrystalline HfO2 based gate stacks. The link between the nanoscale properties and the reliability and gate conduction variability of fully processed MOS devices has also been investigated. Ó 2011 Elsevier B.V. All rights reserved.
1. Introduction Intrinsic process variability and aging mechanisms strongly affect the device performance and reliability, especially in ultrascaled MOS devices [1]. Electrical characteristics of such devices may show large device-to-device variability, which is ultimately associated with the discrete nature of matter and charge. Several variability sources, such as random dopant distribution, among others, have been identified [1]. The homogeneity of the morphological and electrical properties of the high-k gate stack may also be expected to affect the variability of the electrical properties of scaled devices. However, few reports have addressed this topic since standard electrical characterization techniques only provide average information of the complete gate area of fully processed devices [2,3]. On the other hand, during the operation of the device within the circuit, aging mechanisms of the gate dielectric also appear, as defect generation and the dielectric breakdown (BD), which will modify the electrical characteristics of devices. The device aging can introduce large and time-dependent shifts in the parametric figures of devices [4] and circuits [5] and reduce their reliability. To have a more detailed insight on the origin of the variability sources, measurement techniques with a high local resolution are needed in order to study processes at a smaller scale. Scanning probe microscopy and, in particular, Conductive Atomic Force Microscopy (C-AFM), can be used to characterize dielectrics at ⇑ Corresponding author. Tel.: +34 935812517; fax: +34 935812600. E-mail addresses: [email protected], [email protected] (A. Bayerl). 0167-9317/$ - see front matter Ó 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2011.03.122
highly increased resolution [6–9]. In this case, the conductive tip of the C-AFM and the bare gate dielectric stack forms a MOS capacitor with an area of few hundreds of nm2. By applying a voltage, current flows through the structure, which allows evaluating the dielectric electrical properties with nanometer resolution. This technique has been used, for example, to evaluate the impact of some manufacturing processes (like high temperature annealing, which can lead to the gate stack polycrystallization) on the nanoscale electrical properties of high-k dielectrics [10]. However, few works have been devoted to investigate the link between the nanoscale electrical properties and the variability and reliability observed at device level, i.e., on fully processed MOS devices. In this work, a C-AFM and standard wafer level characterization techniques are used in combination to study how the polycrystallization (after a thermal annealing) of the high-k dielectric of MOS capacitors affects their morphological and electrical properties at the nanoscale and the impact of such nanoscale properties on the reliability and variability of the global gate electrical characteristics of fully processed MOS devices. The impact of an electrical stress on the nanoscale and device level properties of amorphous and a polycrystalline structure is also investigated. 2. Experimental The investigated samples consist in MOS capacitors (3 3 lm2) with an Al gate electrode and a HfO2 film as gate dielectric deposited at 225 °C by atomic layer deposition (ALD) on a n-type Si substrate. The oxide thickness, measured by ellipsometry on as deposited dielectrics, was 3.6 nm. Some of the structures were
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annealed at high temperature (TA = 800 °C) to get a polycrystalline high-k layer while others were kept amorphous (annealing at TA = 350 °C). The annealing was performed before gate deposition in an inert nitrogen ambient during 30 min. For both TA, fresh (non-stressed) and stressed (by a Constant Current Stress, CCS, at 5 nA during 300 s or until BD) capacitors were analyzed at the nanoscale and at device level to evaluate the impact of an electrical stress. The variability of the global electrical properties of fully processed MOS devices was analyzed from the measurement of their IG–VG curves with a semiconductor parameter analyzer. The nanoscale electrical properties of some of those structures were investigated with C-AFM (in dry nitrogen ambient and using Pt–Ir coated silicon tips) after the Aluminum gate was removed with a highly selective wet etching. With the C-AFM, current and topography maps were obtained when applying a constant voltage between the tip and the sample during the scan. I–V curves measured at different oxide locations were also registered. Device level and nanoscale measurements were performed on structures coming from the same wafer and the same die, to avoid waferto-wafer and die-to-die variability. 3. Results and discussion
amorphous
polycrystalline
rms:0.11nm
rms:0.18nm
rms:0.15nm
rms:0.37nm
after stress
before stress
To begin with, the impact of the polycrystallization on the nanoscale morphological properties of HfO2 gate stacks was investigated with C-AFM after removing the gate contact. As an example, Fig. 1 shows topographical images of amorphous (a and c) and polycrystalline (b and d) HfO2 layers before (a and b) and after (c and d) being electrically stressed. Before the stress, the polycrystalline sample (Fig. 1b) shows a granular structure (leading to a larger rms value of the surface), which is not observed in Fig. 1a (amorphous). This granularity has been attributed to the presence of randomly orientated nanocrystals separated by grain boundaries (GBs) [10–12], which correspond to the depressed regions in the image. The larger topographical inhomogeneity observed after polycrystallization suggests larger local thickness (tox) fluctuations
within the polycrystalline structures. After the stress (Fig. 1c and d, obtained on amorphous and polycrystalline gate stacks, respectively), the topographical inhomogeneity increases with respect to unstressed samples (Fig. 1a and b). This effect can be probably related to artifacts of the measuring technique associated to charge trapping in the defects generated during the CCS [13]: the trapping/detrapping of elementary charges in/from the defects created during the stress can lead to additional electrostatic interactions between the C-AFM tip and the gate stack. These interactions are interpreted by the C-AFM setup as topographical fluctuations which, actually, are not real. Since Fig. 1 shows, after the stress, a larger increase of the rms value on polycrystalline samples, these results suggest that the spatial distribution of the defects is more inhomogeneous in those samples compared to those that are amorphous. The impact of an electrical stresses on the nanoscale electrical conduction of amorphous and polycrystalline gate stacks has been investigated from the measurement of current images and I–V curves with the C-AFM. Fig. 2 shows, as an example, current images measured by applying the minimum voltage that forces a current just above the noise level on amorphous (a and c) and polycrystalline (b and d) samples before (a and b) and after (c and d) the electrical stress. Note that the current rms value follows the same tendency as surface roughness: polycrystalline samples are more inhomogeneous and the stress has a larger impact on such structures, that is, larger changes in the rms values are measured after the stress. These results are further supported by the measured I–V curves. Fig. 3 shows two sets of I–V characteristics obtained with C-AFM on amorphous (a) and polycrystalline (b) samples, before and after the stress. Table 1 (1st and 2nd rows) indicates the mean value and standard deviation of the gate voltage necessary to measure a current of 10 pA (VI), obtained from the I–V curves in Fig. 3. Note that, the smaller VI, the larger the conductivity of the stack. Fig. 3 and Table 1 show that after the stress, the average electrical conduction is reduced (shift onto larger VI values), probably due to charge trapping in the defects generated during the
2nm
0
amorphous
polycrystalline
rms:0.27pA
rms:0.36pA
rms:0.36pA
rms:4.45pA
after stress
before stress
Fig. 1. Topographical images obtained on the (a and c) amorphous and (b and d) polycrystalline gate stack, before (a and b) an after (c and d) the electrical stress. The surface roughness is also included in the figure.
2pA
0
Fig. 2. Current images obtained on the (a and c) amorphous and (b and d) polycrystalline gate stack, before (a and b) and after (c and d) the electrical stress. The rms value before and after the electrical stress is also included.
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Fig. 3. I–V curves obtained with CAFM, before and after the stress, on the (a) amorphous and (b), polycrystalline annealed samples. The area of the MOS structure under analysis is determined by the tip-sample contact region, which is of the order of few hundreds of nm2.
Nanoscalr 10 pA
hVIi (V)
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hVIi (V)
r (mV)
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Polycrystalline
Fresh
Stressed
Fresh
Stressed
3.74 129
4.09 154
5.72 247
6.61 343
0.86 4.2
0.87 4.9
0.25 110
– –
CCS. Moreover, again, the dispersion increases and becomes much larger after the stress in polycrystalline samples. This effect could be related to the different electrical properties between GBs and nanocrystals in polycrystalline structures. GBs, probably with an initial excess of some kind of native defects (generated during polycrystallization), could be even more affected by the electrical stress, leading to larger fluctuations of the electrical conduction after the stress, detected as an increase of the conductivity deviation (Table 1 and Fig. 3). Therefore, the results obtained with CAFM show that the polycrystallization of the high-k layer is an important source of nanoscale electrical variability, which further increases after an electrical stress. But, how does this nanoscale variability affect the performance of MOS devices? In this section, in an effort to evaluate the impact of the previously analyzed nanoscale variability sources and the
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10
-12
10
-10
10
-13
10
-11
10
-11
10
-12
10 1.5
-12
10 3.0
-14
1,5
2.5
-4
10
-10
-8
1.5
10
10
5x10
1.0
1.5 -3 10
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-7
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1.0
10
10
1,4
0.5
-3
10 -7
1,5x10
1,3
0.0
10
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IG [V]
IG [A]
(a)
effect of an electrical stress on the global electrical properties and reliability of MOS capacitors, some of the fully-processed devices have been investigated with standard characterization techniques. In particular, the gate conduction and the electric field at breakdown (EBD) has been evaluated from the I–V characteristics measured before and after the electrical stress. Fig. 4 shows some I–V characteristics measured on the amorphous (a) and polycrystalline (b) Al-gated capacitors, before (squares) and after (triangles) the stress. The mean value and dispersion of the onset voltage, VI, necessary to detect a current of 1 nA has been used to quantify oxide conductivity (Table 1, rows 3 and 4). At device level (after the stress), in the polycrystalline samples, no data is added since all capacitors were broken down during the stress and post-BD currents are larger than 1 nA (at very low voltages, see Fig. 4b). First, it must be noted that a direct comparison between the currents in Fig. 4a (capacitors data) and Fig. 3a (CAFM data) is not meaningful, because experimental factors (such as changes on the tip conductivity, contact area, small variations of the oxide thickness or different gate electrodes) can affect the value of the measured current. However, since we are only interested in relative variations of conductivity, the experimental related differences do not change the conclusions of the work. In Fig. 4a (amorphous), those capacitors that do not break down during the CCS show a reduction of the electrical conduction and an increment of the dispersion (Table 1) compared to fresh structures. Both effects could be related to the random generation of defects during the stress, which could trap charge (shift onto higher voltages) and modify locally the gate stack conductivity (larger fluctuations). In (b), (polycrystalline samples), before the stress,
0.0
before stress after stress
0.5
1.0
VG [V]
(c) 2
cumulative failure ln(-ln(1-F))
Table 1 Mean value and deviation of the gate voltage (VI) necessary to measure a current of 10 pA (nanoscale measurements) and 1 nA (device level measurements), obtained from the I–V curves in Figs. 3 and 4, respectively. At device level, in the polycrystalline sample, no data is added since all capacitors were broken down during the stress and post-BD currents are larger than 1 nA for very low voltages.
2.5
5.0
7.5
10.0
12.5
15.0 2 1
1 polycristalline
0
0 amorphous
-1
-1
-2
-2
-3
-3
-4
-4
-5
2.5
5.0
7.5
10.0
12.5
-5 15.0
EBD [MV/cm]
Fig. 4. I–V curves obtained on Al-gated structures (3 3 lm2), before (squares) and after (triangles) the stress, on the (a) amorphous and (b) polycrystalline samples. (c) Shows the EBD Weibull distribution of the different samples when subjected to RVS.
A. Bayerl et al. / Microelectronic Engineering 88 (2011) 1334–1337
the gate conduction is larger and shows a higher dispersion than that in amorphous gate dielectrics (Fig. 4a), probably due to presence of grain boundaries, which have been found to be leakier [10]. Moreover, all of the capacitors broke down during the CCS. Actually, Fig. 4c shows the EBD Weibull distributions of the analyzed structures when subjected to ramped voltage stress (RVS). The results show smaller values and larger dispersions of EBD after polycrystallization. Therefore, these results indicate that polycrystalization of the high-k layer not only affects the variability of the electrical properties of MOS devices, but also their reliability. 4. Conclusions In this work, the relation between the nanoscale and device level gate conduction variability and reliability of MOS devices based on amorphous and polycrystalline HfO2 gate stacks has been studied. Polycrystallization of high-k dielectrics increases the inhomogeneity of the nanoscale surface morphology, conductivity and trapping properties, which is enhanced after an electrical stress. These nanoscale inhomogeneities are transferred to the global gate electrical properties of fully processed MOS devices. In particular, gate current variability increases much more in polycrystalline samples. Moreover, a reduction of their reliability is also measured. The results show that the larger the initial (before any stress) variability of the gate stacks properties (due to polycrytallization of high-k dielectrics, in this work), the larger the impact of an electrical stress on their nanoscale and device level electrical properties and reliability.
1337
Acknowledgements This work has been partially supported by the Spanish MICINN (TEC2007-61294, TEC2010-16126 and GICSERV5-NGG120) and the Generalitat de Catalunya (2009SGR-783). References [1] A. Asenov, S. Roy, R.A. Brown, G. Roy, C. Alexander, C. Riddet, C. Millar, B. Cheng, A. Martinez, N. Seoane, D. Reid, M.F. Bukhori, X. Wang, U. Kovac, IEEE Electron Device Meet. Tech. Digest (2008). [2] J. Robertson, Rep. Prog. Phys. 69 (2006) 327–396. [3] R. Degraeve, M. Aoulaiche, B. Kaczer, P. Roussel, T. Kauerauf, S. Sahhaf, G. Groeseneken, Proc. 15th Phys. Failure Anal. Integr. Circuits (IPFA) (2008) 1–6. [4] M. Alam, Microbiol. Reliab. 9 (2008) 1114–1122. [5] W. Hua, M. Miranda, F. Catthoor, W. Dehaene, IEEE Trans. Device Mater. Reliab. 7 (4) (2007) 581–591. [6] Y.L. Wu, S.T. Lin, C.P. Lee, IEEE Trans. Device Mater. Reliab. 8 (2) (2008) 352– 357. [7] P. Fiorenza, W. Polspoel, W. Vandervorst, Appl. Phys. Lett. 88 (22) (2006). Art. No. 222104. [8] M. Lanza, M. Porti, M. Nafría, X. Ayermich, A. Sebastiani, G. Ghidini, A. Vedda, M. Fasoli, IEEE Trans. Device Mater. Reliab. 9 (4) (2009). [9] W. Frammelsberger, G. Benstetter, Appl. Surf. Sci. 252 (6) (2006) 2375–2388. [10] V. Iglesias, M. Porti, M. Nafría, X. Aymerich, P. Dudek, T. Schroeder, G. Bersuker, Appl. Phys. Lett. 97 (26) (2010) 262906. [11] V. Yanev, M. Rommel, M. Lemberger, S. Petersen, B. Amon, T. Erlbacher, A.J. Bauer, H. Ryssel, A. Paskaleva, W. Weinreich, C. Fachmann, J. Heitmann, U. Schroeder, Appl. Phys. Lett. 92 (25) (2008). [12] P. Gusev, C. Cabral Jr., M. Copel, Microelectron. Eng. 69 (2–4) (2003) 145–151. [13] M. Porti, M. Nafría, M.C. Blüm, X. Aymerich, Appl. Phys. Lett. 81 (19) (2002) 3615–3617.