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Strategy for preparation of transparent organic thin film transistors with PEDOT:PSS electrodes and a polymeric gate dielectric
Materials Science in Semiconductor Processing 40 (2015) 772–776
Contents lists available at ScienceDirect
Materials Science in Semiconductor Processing journal homepage: www.elsevier.com/locate/matsci
Strategy for preparation of transparent organic thin film transistors with PEDOT:PSS electrodes and a polymeric gate dielectric G. Albrecht, S. Heuser, C. Keil, D. Schlettwein n Justus-Liebig-University Giessen, Institute of Applied Physics and Laboratory of Materials Research, Heinrich-Buff-Ring 16, D-35394 Gießen, Germany
art ic l e i nf o
a b s t r a c t
Article history: Received 20 July 2015 Accepted 21 July 2015
Fully transparent organic field effect transistors (OFET) in top- and bottom-gate layouts were prepared. Poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS) was structured photolithographically as either gate- or source- and drain-contact on top of poly(4-vinylphenol) (PVP). The dielectric material was fitted to the sequence of materials by combining water soluble polyvinyl alcohol (PVA) and PVP. N-type conducting hexadecafluorophthalocyaninato-copper (F16PcCu) was used as organic semiconductor sensitive to interface traps. Critical boundary surfaces for film growth were examined by microscopic methods, which revealed smooth polymer surfaces as a result of our preparation and lithography steps characterizing the presented concept as a viable alternative to existing approaches. & 2015 Elsevier Ltd. All rights reserved.
Keywords: Organic field-effect transistor Dielectric layer Polymer Photolithography Transparent device Poly(3,4-ethylenedioxythiophene) polystyrene sulfonate
1. Introduction Organic field-effect transistors (OFET) are an integral part of the promising field of organic electronics. The unique properties of organic materials compared to the established inorganic semiconductors may allow cost effective, large area fabrication techniques, e.g., printing [1], stamping or photolithography [2]. Recent studies have shown that electrical properties of organic electronic devices like the field-effect mobility of OFETs can be comparable to those of amorphous Si thin-film transistors (TFT) [3]. Organic electronics and in particular OFET, therefore, are a relevant topic for research since they can serve as a basis for technical applications like displays, human–machine interfaces, smart digital gadgets, memory devices or ID-tags [4]. For some of these applications transparency is a relevant property to open up new possibilities in the design of devices and, hence, establish additional quality and value. A good such example can be seen in the placement of FETs in active matrix displays as pixel-driving component [5]. Until recently, in transparent OFETs they mainly had to consist of oxides such as SnO2, ZnO, In2O3 or ternary compounds of them [6]. These materials generally need conditioning at high temperature posing limitations to the choice of substrate materials. In order to construct flexible, lightweight devices, the use of temperature-sensitive polymers, however, would be highly desirable and compatible with the use of organic n
Corresponding author. E-mail address: [email protected] (D. Schlettwein).
http://dx.doi.org/10.1016/j.mssp.2015.07.057 1369-8001/& 2015 Elsevier Ltd. All rights reserved.
semiconductors (OSCs) in the logic circuit. Therefore a growing interest in incorporating OSCs into the field of transparent electronics can be noticed [7–10]. This may then allow the development of applications such as all organic flexible displays [4] or transparent sensors [11]. The establishment of flexible microelectronics requires low-temperature processes in order to avoid damaging of polymeric substrates, e.g., below at most 250–260 °C if polyethylene terephthalate (PET) is going to be used [12,13]. In order to establish efficiently working devices, structuring methods like photolithography or printing have to be developed, which are compatible with the use of soft matter like polymer insulators or OSCs. Although printing is less demanding in many cases and allows extensive customization of devices photolithography holds the advantage of allowing optimized structure size. Many of the recent advances in the preparation of transparent OFETs rely on the use of inorganic source and drain electrodes [7,9,10,14,15]. As indicated above, such layers generally require high annealing temperatures (in case of oxides) or lead to a significant loss of transparency (in case of metals). When deposited on top of an organic layer even metals can easily induce damage of the soft material. As a possible alternative to inorganic contacts, a mixture of poly(3,4-ethylenedioxy-thiophene) and poly(styrene sulfonate) (PEDOT:PSS) represents a well-known conductive polymer, which is, e.g., already used in solid electrolyte capacitors, touch screens, organic light emitting diodes (OLEDs) and organic photovoltaic cells [16]. Thin films of PEDOT:PSS can reach a conductivity of up to 1000 S/cm while retaining a transmission of up
G. Albrecht et al. / Materials Science in Semiconductor Processing 40 (2015) 772–776
to 95% [17]. PEDOT:PSS provides higher mechanical flexibility than transparent conductive oxides like indium tin oxide (ITO), often used as a transparent conductor in the field [18]. Furthermore, PEDOT:PSS enables lower embedded energy and production costs [19]. For medical applications, the recently reported biocompatibility of PEDOT:PSS thin films may also be relevant [20]. Since PEDOT:PSS conductive thin films can be processed from solution, a recent focus in research can be seen on printing PEDOT:PSS films at optimized resolution for the obtained structures [21,22]. To complement such low-temperature approaches to the conductive electrodes, insulating polymers can also be used as gate dielectrics in OFET structures. Poly(vinyl alcohol) (PVA) can serve as polymeric insulator with a dielectric constant of εr ¼10.4, attractively higher than that of poly(methyl methacrylate) (PMMA, ε r ¼3.5) or poly(4-vinylphenol) (PVP, εr ¼4.5), also often used in the field [23]. PVA und PVP thin films have also been combined to form a double dielectric layer, uniting the advantageous εr of PVA with the water resistance of PVP [24]. In the present paper we propose an approach to transparent OFETs by providing two complementary layering orders in either top-contact/bottom-gate or bottom-contact/top-gate geometry. The gate dielectric was designed to allow both processes needed in these approaches, semiconductor film growth or photolithographic structuring of PEDOT:PSS, used as solution-processed contact material. A combination of PVP and PVA films served as dielectric layer. The temperature during preparation was consequently kept below 200 °C to allow a possible transfer of the methods to flexible substrates. For practical reasons, however, ITOcoated glass was used as a substrate throughout this study.
2. Materials and methods PEDOT:PSS (Clevios™ PH1000) was purchased from Heraeus and two solutions, containing 5% dimethyl sulfoxide (DMSO) and either 1% Brij C10 or 1% Pluronic P123, both bought from Sigma Aldrich, were prepared for spin-coating of films as described in detail below. Mowiol 40-88 was purchased from Sigma Aldrich and dissolved in doubly-distilled water to prepare a 10% PVA solution. The PVP solution, based on the work of Chang et al. [24], contained 550 mg PVP and 220 mg poly(melamine-co-formaldehyde) (PMCF) dissolved in 5 ml propylene glycol monomethyl ether acetate (PGMEA), obtained from Sigma Aldrich. As developer and photoresist ma-D 311 and ma-P 1215 from micro resist technology were used, respectively. Acetone ( Z99.8), isopropanol ( Z99.8), ethanol (Z 99.8), hydrochloric acid (37%) and nitric acid (65%) were purchased from CARL ROTH GMBH þCO. KG. Hexadecafluorophthalocyaninato-copper (F16PcCu) was obtained from Tokyo Chemical Industry CO. LTD. with a purity of 4 98%. All transistors were structured on CG-50IN-S115 glass coated with indium tin oxide (ITO) from Delta Technologies Lim. The substrates were cleaned for 5 minu each in acetone, isopropanol and ethanol by use of an ultrasonic bath. The photolithographic steps followed a common protocol under cleanroomconditions: resist was spun on at 3000 rpm for 30 s, followed by a hot plate bake at 100 °C for 90 s. In case of the bottom-contact/ top-gate FETs, after 90 s exposure to UV-light in a UV-box through a Cr-mask, a positive image of the desired pattern was developed for 40 s followed by a three minutes post-exposure bake at 100 °C. For the top-contact/bottom-gate FETs, exposure through the maskaligner lasted 9.5 s. Etching of ITO following the photolithographic masking of the desired structure details was conducted in a solution of HCl, HNO3 and distilled water in a 4:1:3 ratio for 15 min at room temperature. Afterwards, the remaining photoresist was removed in acetone. F16PcCu was deposited at 0.3–0.8 nm min 1 rate by evaporation from a resistively heated boron nitride crucible
773
(Lesker) at 10 6 mbar. Optical microscopy images of the transistor channel were taken by a Keyence VK-9710 3D confocal laser-microscope. Height information of the thin films was measured with a Tencor Instruments α-step profilometer. Atomic force microscopy (AFM) was performed with an AIST-NT SmartSPM 1000 in intermittent contact mode and scanning electron microscopy (SEM) with a Carl Zeiss SMT MERLIN. For the electrical measurements at the field effect transistors (in vacuum, 10 6 mbar) and for the resistance measurement of the insulating channel, a Keithley 487 Picoamperemeter and a Keithley 6430 SUB-FEMTOAMP remote SourceMeter were used. Photographs of the OFETs were taken with a NIKON D40 digital SLR. Photolithography was performed by use of a Süss MicroTec maskaligner MA 56 and a home-built UVbox. A UNI-Trend UT61C was used to probe resistance. The thickness of the semiconductor films was measured in-situ by use of a calibrated quartz crystal micro-balance.
3. Results and discussion The gate dielectric can be considered a key component of any thin film transistor. In addition to its insulating purpose, the interface with the semiconducting layer has to be optimized in order to avoid excessive trapping of charge, hence limiting the performance of the device. Furthermore, the insulator needs to be sufficiently thin in order to allow high source-drain currents at low gate voltages. Aside from a high permittivity, additional characteristics may become essential to allow the preparation of subsequent layers and the formation of suitable contacts. Since PEDOT:PSS, e.g., is water-soluble [21], adjacent layers formed beforehand or subsequently should not show hydrophilic characteristics to avoid dissolution of already existing layers. In order to establish different OFET structures the gate insulator has to be adopted in these characteristics to the sequence of layers in the device. A bottom-contact/top-gate geometry can be advantageous if the OSC has to be protected from the environment containing, e.g., oxygen or humidity, since the insulator encapsulates the OSC in such geometry. Further, since source and drain electrodes are prepared before any other layers of the device, a broad spectrum of materials and related processes becomes available. If, however, the OSC layer has to be exposed to the environment because, e.g., the OFET is meant to act as a chemical sensor, a top-contact/bottomgate TFT is the preferred design. Therefore, strategies for both design principles have been developed here. 3.1. Bottom-contact/top-gate FET The design of our bottom-contact/top-gate FET can be seen in Fig. 1a. F16PcCu, the semiconducting layer, is directly encapsulated by the polymeric insulator to shield it from the influence of the surroundings. F16PcCu was deposited onto the microstructured ITO source and drain contacts schematically shown in Fig. 1b. Optimizing the etching process provided a clean ITO interdigitated electrode array with good resolution, as seen in Fig. 1c. In order to avoid any remaining conductive pathways of ITO on the unmasked parts of the pattern, i.e., the transistor channel, the etching process was optimized to provide a resistance of the glass between the contacts of at least 60 MΩ. Since this etched glass surface also served as a substrate to grow the semiconductor layer and since the interface between the glass and the semiconductor, further, will critically determine the properties of the transistor channel, the glass surface was analyzed in detail. Fig. 2a shows the topography of this glass surface in between the ITO source and drain contacts as revealed by atomic force microscopy (AFM). The surface is seen to be quite smooth,
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Fig. 1. Side view of the layer structure of the bottom-contact/top-gate FET (a) and corresponding source drain electrode pattern (b) as a scheme and laser-microscopy image (c).
scanning electron microscopy (SEM). A continuous film, widely free of pinholes was formed with grain size and morphology widely uniform on the whole surface, indicating good film quality. In the next step of device preparation, a solution of PVA was spun onto the F16PcCu semiconductor film at 1000 rpm for 30 s and cured at 90 °C for 12 h, resulting in a 900 nm thick film. Subsequently, a solution of PVP was used for spin-coating at 1000 rpm for 30 s. The samples were then heated to 120 °C on a hot plate and cured at 200 °C for 20 min. The film thickness of PVP was measured to be 500 nm. The addition of the cross-linking agent PMCF to the PVP solution is advantageous for preparing thin films because the formation of holes in the surface is minimized in cross-linked films [25]. To further avoid leakage currents through the insulator, we used rather thick insulating layers of up to 1.4 mm. To complete the device, the PEDOT:PSS-solution containing Brij C10 was spun on at 3000 rpm for 30 s and cured at 100 °C for 10 s to dry the film and to remove the remaining solvent, leading to a layer of 150 nm thickness and a sheet resistance of 1.5 kΩ cm 1. Brij C10 was added to the aqueous PEDOT:PSS solution to increase wetting and, hence, adherence of the film to the hydrophobic PVP surface. Fig. 3a shows the electrical characteristics of a successfully prepared OFET with a channel width of 10 mm and length of 3 cm. A field-effect mobility of 1.5 10 6 cm2 V 1 s 1was determined for the F16PcCu semiconductor in the channel. A working transistor was achieved at, however, an on/off ratio of only 12. Other FETs of the same structure but with a channel width of 40 mm and a length of 6 cm prepared in this study showed similar on/off at, however, improved mobility values of up to 6.6 10 4 cm2 V 1 s 1. The corresponding characteristics are shown in Fig. 3c. The mobility determined in the present devices fits well to those determined earlier for films of F16PcCu which were prepared
Fig. 2. Atomic force microscopy image of the glass surface after etching off ITO (a) with height range as indicated in the figure and scanning electron microscopy image of the F16PcCu layer deposited into the transistor channel (b).
with some grains of about 13 nm height. This surface served as substrate to grow the semiconducting channel of F16PcCu. Fig. 2b shows the structure of a 30 nm thin film of the semiconductor F16PcCu in the transistor channel as revealed by
Fig. 3. Electrical characteristics (a, c) and photograph (b) of finished bottom-contact/top-gate FETs.
G. Albrecht et al. / Materials Science in Semiconductor Processing 40 (2015) 772–776
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Fig. 4. Side view of the layer structure of the top-contact/bottom gate FET (a), corresponding source drain electrode pattern with contact pads (b) and laser-microscopy image of the processed electrodes and transistor channel (c).
by the same method, but on the oxidized surface of a silicon wafer [26], which gave values for the electron mobility around 1 10 3 cm2 V 1 s 1. The thickness of the gate insulator in these studies was 300 nm, so in direct comparison, the field-effect is higher and as expected, leads to on/off ratios around 104. A photograph of a complete OFET in our bottom-contact/topgate geometry can be seen in Fig. 3b. Good optical transparency is already noted by eye and a transmittance between 70 and 80 percent was measured by spectrometry in the visible range. The brown tint is caused by the PVA film, which changed color during the thermal treatment, used for curing of the PVP layer. 3.2. Top-contact/bottom gate FET
Fig. 5. Atomic force microscopy images of the PVP-surface (a) below the F16PcCu film (b) in the transistor channel of the top-contact/bottom gate OFET.
Fig. 4a shows a schematic representation of the top-contact/ bottom-gate FETs prepared in this study. As intended, the semiconductor layer is prepared on top of the structure, for example enabling its use for sensing purposes. Further, the addition of the semiconductor layer represents the last step of device preparation avoiding any possible contamination or process damage to the semiconductor film which often consists of quite sensitive materials. The bilayer insulator substrate, furthermore, has the advantage of easy adaptability to other adjacent materials, should the need arise, by either providing a hydrophilic or hydrophobic surface in regards to specific layer designs. The ITO-covered glass substrates were etched to leave a 4 mm wide strip of ITO as gate electrode. A PVA-solution was spun on at 2000 rpm for 30 s and the film was cured at 120 °C for five minutes leaving 150 nm thick PVA. The PVP-solution was spun on at 2000 rpm for 30 s heated to 120 °C and then cured at 200 °C for five minutes, resulting in 350 nm thick PVP. This change in preparation protocol compared to the 20 min curing for the bottomcontact/top-gate TFT led to a dielectric without a colored tint and still sufficiently stable to the subsequent process steps. A negative of the desired source and drain pattern, as seen in Fig. 4b, was developed via photolithography. A microscopic image of the resulting transistor channel is shown in Fig. 4c. The edges of the PEDOT:PSS electrodes are even and the channel width is 55 mm. The substrates were then exposed to a UV/ozone treatment for five minutes in order to allow good adhesion of PEDOT:PSS. To make sure the PVP-surface is suitable to the growth of a compact semiconducting layer of good quality, the surface topography was analyzed by AFM. Fig. 5a shows a PVP-surface
following photolithography and UV/ozone treatment. The surface was measured to be quite homogeneous and flat, except a few grains of about 10 nm height. Since grains of a similar size were seen in Fig. 2a, the glass surface following photolithography and etching, these might consist of remaining photoresist. The PVP surface shows no features of any higher roughness than the glass surface. It is seen that the present preparation steps provide a process which is suitable to prepare structures with sufficient homogeneity to provide appropriate interfaces between insulator and semiconductor. PEDOT:PSS from the solution containing P123 was spun on at 3000 rpm for 30 s and immediately dried at 100 °C for 10 min, leading to a 150 nm thick film. The remaining photoresist was removed in a lift-off using acetone. The substrates were transferred to vacuum where the organic semiconductor F16PcCu was deposited at an average film thickness of 20 nm in the final preparation step. The devices were left in vacuum at room temperature for three days in order to condition the semiconductor towards higher film quality and improved performance as indicated in previous work [26]. The quality of the semiconductor layer was also investigated by atomic force microscopy, shown in Fig. 5b. As seen on glass before (Fig. 2b), film growth occurred in a very uniform way also on this polymer substrate. The surface showed height fluctuations of only up to 10 nm, less than the average film thickness of 20 nm. The grains are uniform in size and shape and form a continuous film without pinholes or obvious discontinuities, providing a semiconductor suitable for OFET with good conduction pathways as also obtained in earlier studies which showed a similar morphology of F16PcCu thin films [26].
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[2]
[3] [4]
[5]
[6] [7]
[8] Fig. 6. Output characteristics of a finished top-contact/bottom gate FET directly after deposition of F16PcCu (a). A photograph of the device is shown as inset (b).
The output characteristics of a device prepared in top-contact/ bottom gate OFET geometry directly after deposition of F16PcCu are shown in Fig. 6a providing a field-effect mobility of 1.5 10 4 cm2 V 1 s 1 and an on/off ratio of 22. These values are quite similar to the values measured for the bottom-contact/topgate devices despite a larger grain size and, hence, less grain boundaries which should lead to improved properties in the topcontact/bottom-gate structure. This effect, however, might be compensated by the influence of the interface area of the semiconductor and the dielectric material. An increased density of electron traps is detrimental to the carrier transport and, thus, can be the cause of the lower mobility we observed. A photograph of the device prepared in top-contact/bottomgate geometry is shown as an inset of Fig. 6a. Optical transparency as observed by eye was measured between 70% and 85%, similar to the values for the devices in bottom-contact/top-gate geometry shown above. The brown tint present in the latter geometry could be avoided by a shorter curing time.
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
4. Conclusions In conclusion, we have presented strategies to prepare almost ideally transparent organic field-effect transistors using low temperatures and yielding functional microelectronics, demonstrated here for devices in either bottom-contact/top-gate or top-contact/ bottom-gate geometry. The processes established here on ITOcoated glass are well compatible with the use of mechanically flexible ITO-coated polymer substrates, e.g., ITO on PET. The two complementary layering approaches open up a wide range of application possibilities. By the combination of hydrophilic and hydrophobic insulating materials, a range of semiconducting materials and/or contact materials can be chosen. It was shown that the different thin films can be prepared with good quality in the different sequences. Furthermore, it was shown that PEDOT:PSS can be patterned by photolithography on top of a PVP-layer which may be of relevance to the preparation of a variety of organic transparent electronic devices, also beyond the field of OFET.
[18] [19]
[20]
[21] [22]
[23] [24]
[25]
[26]
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Contents lists available at ScienceDirect
Materials Science in Semiconductor Processing journal homepage: www.elsevier.com/locate/matsci
Strategy for preparation of transparent organic thin film transistors with PEDOT:PSS electrodes and a polymeric gate dielectric G. Albrecht, S. Heuser, C. Keil, D. Schlettwein n Justus-Liebig-University Giessen, Institute of Applied Physics and Laboratory of Materials Research, Heinrich-Buff-Ring 16, D-35394 Gießen, Germany
art ic l e i nf o
a b s t r a c t
Article history: Received 20 July 2015 Accepted 21 July 2015
Fully transparent organic field effect transistors (OFET) in top- and bottom-gate layouts were prepared. Poly(3,4-ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS) was structured photolithographically as either gate- or source- and drain-contact on top of poly(4-vinylphenol) (PVP). The dielectric material was fitted to the sequence of materials by combining water soluble polyvinyl alcohol (PVA) and PVP. N-type conducting hexadecafluorophthalocyaninato-copper (F16PcCu) was used as organic semiconductor sensitive to interface traps. Critical boundary surfaces for film growth were examined by microscopic methods, which revealed smooth polymer surfaces as a result of our preparation and lithography steps characterizing the presented concept as a viable alternative to existing approaches. & 2015 Elsevier Ltd. All rights reserved.
Keywords: Organic field-effect transistor Dielectric layer Polymer Photolithography Transparent device Poly(3,4-ethylenedioxythiophene) polystyrene sulfonate
1. Introduction Organic field-effect transistors (OFET) are an integral part of the promising field of organic electronics. The unique properties of organic materials compared to the established inorganic semiconductors may allow cost effective, large area fabrication techniques, e.g., printing [1], stamping or photolithography [2]. Recent studies have shown that electrical properties of organic electronic devices like the field-effect mobility of OFETs can be comparable to those of amorphous Si thin-film transistors (TFT) [3]. Organic electronics and in particular OFET, therefore, are a relevant topic for research since they can serve as a basis for technical applications like displays, human–machine interfaces, smart digital gadgets, memory devices or ID-tags [4]. For some of these applications transparency is a relevant property to open up new possibilities in the design of devices and, hence, establish additional quality and value. A good such example can be seen in the placement of FETs in active matrix displays as pixel-driving component [5]. Until recently, in transparent OFETs they mainly had to consist of oxides such as SnO2, ZnO, In2O3 or ternary compounds of them [6]. These materials generally need conditioning at high temperature posing limitations to the choice of substrate materials. In order to construct flexible, lightweight devices, the use of temperature-sensitive polymers, however, would be highly desirable and compatible with the use of organic n
Corresponding author. E-mail address: [email protected] (D. Schlettwein).
http://dx.doi.org/10.1016/j.mssp.2015.07.057 1369-8001/& 2015 Elsevier Ltd. All rights reserved.
semiconductors (OSCs) in the logic circuit. Therefore a growing interest in incorporating OSCs into the field of transparent electronics can be noticed [7–10]. This may then allow the development of applications such as all organic flexible displays [4] or transparent sensors [11]. The establishment of flexible microelectronics requires low-temperature processes in order to avoid damaging of polymeric substrates, e.g., below at most 250–260 °C if polyethylene terephthalate (PET) is going to be used [12,13]. In order to establish efficiently working devices, structuring methods like photolithography or printing have to be developed, which are compatible with the use of soft matter like polymer insulators or OSCs. Although printing is less demanding in many cases and allows extensive customization of devices photolithography holds the advantage of allowing optimized structure size. Many of the recent advances in the preparation of transparent OFETs rely on the use of inorganic source and drain electrodes [7,9,10,14,15]. As indicated above, such layers generally require high annealing temperatures (in case of oxides) or lead to a significant loss of transparency (in case of metals). When deposited on top of an organic layer even metals can easily induce damage of the soft material. As a possible alternative to inorganic contacts, a mixture of poly(3,4-ethylenedioxy-thiophene) and poly(styrene sulfonate) (PEDOT:PSS) represents a well-known conductive polymer, which is, e.g., already used in solid electrolyte capacitors, touch screens, organic light emitting diodes (OLEDs) and organic photovoltaic cells [16]. Thin films of PEDOT:PSS can reach a conductivity of up to 1000 S/cm while retaining a transmission of up
G. Albrecht et al. / Materials Science in Semiconductor Processing 40 (2015) 772–776
to 95% [17]. PEDOT:PSS provides higher mechanical flexibility than transparent conductive oxides like indium tin oxide (ITO), often used as a transparent conductor in the field [18]. Furthermore, PEDOT:PSS enables lower embedded energy and production costs [19]. For medical applications, the recently reported biocompatibility of PEDOT:PSS thin films may also be relevant [20]. Since PEDOT:PSS conductive thin films can be processed from solution, a recent focus in research can be seen on printing PEDOT:PSS films at optimized resolution for the obtained structures [21,22]. To complement such low-temperature approaches to the conductive electrodes, insulating polymers can also be used as gate dielectrics in OFET structures. Poly(vinyl alcohol) (PVA) can serve as polymeric insulator with a dielectric constant of εr ¼10.4, attractively higher than that of poly(methyl methacrylate) (PMMA, ε r ¼3.5) or poly(4-vinylphenol) (PVP, εr ¼4.5), also often used in the field [23]. PVA und PVP thin films have also been combined to form a double dielectric layer, uniting the advantageous εr of PVA with the water resistance of PVP [24]. In the present paper we propose an approach to transparent OFETs by providing two complementary layering orders in either top-contact/bottom-gate or bottom-contact/top-gate geometry. The gate dielectric was designed to allow both processes needed in these approaches, semiconductor film growth or photolithographic structuring of PEDOT:PSS, used as solution-processed contact material. A combination of PVP and PVA films served as dielectric layer. The temperature during preparation was consequently kept below 200 °C to allow a possible transfer of the methods to flexible substrates. For practical reasons, however, ITOcoated glass was used as a substrate throughout this study.
2. Materials and methods PEDOT:PSS (Clevios™ PH1000) was purchased from Heraeus and two solutions, containing 5% dimethyl sulfoxide (DMSO) and either 1% Brij C10 or 1% Pluronic P123, both bought from Sigma Aldrich, were prepared for spin-coating of films as described in detail below. Mowiol 40-88 was purchased from Sigma Aldrich and dissolved in doubly-distilled water to prepare a 10% PVA solution. The PVP solution, based on the work of Chang et al. [24], contained 550 mg PVP and 220 mg poly(melamine-co-formaldehyde) (PMCF) dissolved in 5 ml propylene glycol monomethyl ether acetate (PGMEA), obtained from Sigma Aldrich. As developer and photoresist ma-D 311 and ma-P 1215 from micro resist technology were used, respectively. Acetone ( Z99.8), isopropanol ( Z99.8), ethanol (Z 99.8), hydrochloric acid (37%) and nitric acid (65%) were purchased from CARL ROTH GMBH þCO. KG. Hexadecafluorophthalocyaninato-copper (F16PcCu) was obtained from Tokyo Chemical Industry CO. LTD. with a purity of 4 98%. All transistors were structured on CG-50IN-S115 glass coated with indium tin oxide (ITO) from Delta Technologies Lim. The substrates were cleaned for 5 minu each in acetone, isopropanol and ethanol by use of an ultrasonic bath. The photolithographic steps followed a common protocol under cleanroomconditions: resist was spun on at 3000 rpm for 30 s, followed by a hot plate bake at 100 °C for 90 s. In case of the bottom-contact/ top-gate FETs, after 90 s exposure to UV-light in a UV-box through a Cr-mask, a positive image of the desired pattern was developed for 40 s followed by a three minutes post-exposure bake at 100 °C. For the top-contact/bottom-gate FETs, exposure through the maskaligner lasted 9.5 s. Etching of ITO following the photolithographic masking of the desired structure details was conducted in a solution of HCl, HNO3 and distilled water in a 4:1:3 ratio for 15 min at room temperature. Afterwards, the remaining photoresist was removed in acetone. F16PcCu was deposited at 0.3–0.8 nm min 1 rate by evaporation from a resistively heated boron nitride crucible
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(Lesker) at 10 6 mbar. Optical microscopy images of the transistor channel were taken by a Keyence VK-9710 3D confocal laser-microscope. Height information of the thin films was measured with a Tencor Instruments α-step profilometer. Atomic force microscopy (AFM) was performed with an AIST-NT SmartSPM 1000 in intermittent contact mode and scanning electron microscopy (SEM) with a Carl Zeiss SMT MERLIN. For the electrical measurements at the field effect transistors (in vacuum, 10 6 mbar) and for the resistance measurement of the insulating channel, a Keithley 487 Picoamperemeter and a Keithley 6430 SUB-FEMTOAMP remote SourceMeter were used. Photographs of the OFETs were taken with a NIKON D40 digital SLR. Photolithography was performed by use of a Süss MicroTec maskaligner MA 56 and a home-built UVbox. A UNI-Trend UT61C was used to probe resistance. The thickness of the semiconductor films was measured in-situ by use of a calibrated quartz crystal micro-balance.
3. Results and discussion The gate dielectric can be considered a key component of any thin film transistor. In addition to its insulating purpose, the interface with the semiconducting layer has to be optimized in order to avoid excessive trapping of charge, hence limiting the performance of the device. Furthermore, the insulator needs to be sufficiently thin in order to allow high source-drain currents at low gate voltages. Aside from a high permittivity, additional characteristics may become essential to allow the preparation of subsequent layers and the formation of suitable contacts. Since PEDOT:PSS, e.g., is water-soluble [21], adjacent layers formed beforehand or subsequently should not show hydrophilic characteristics to avoid dissolution of already existing layers. In order to establish different OFET structures the gate insulator has to be adopted in these characteristics to the sequence of layers in the device. A bottom-contact/top-gate geometry can be advantageous if the OSC has to be protected from the environment containing, e.g., oxygen or humidity, since the insulator encapsulates the OSC in such geometry. Further, since source and drain electrodes are prepared before any other layers of the device, a broad spectrum of materials and related processes becomes available. If, however, the OSC layer has to be exposed to the environment because, e.g., the OFET is meant to act as a chemical sensor, a top-contact/bottomgate TFT is the preferred design. Therefore, strategies for both design principles have been developed here. 3.1. Bottom-contact/top-gate FET The design of our bottom-contact/top-gate FET can be seen in Fig. 1a. F16PcCu, the semiconducting layer, is directly encapsulated by the polymeric insulator to shield it from the influence of the surroundings. F16PcCu was deposited onto the microstructured ITO source and drain contacts schematically shown in Fig. 1b. Optimizing the etching process provided a clean ITO interdigitated electrode array with good resolution, as seen in Fig. 1c. In order to avoid any remaining conductive pathways of ITO on the unmasked parts of the pattern, i.e., the transistor channel, the etching process was optimized to provide a resistance of the glass between the contacts of at least 60 MΩ. Since this etched glass surface also served as a substrate to grow the semiconductor layer and since the interface between the glass and the semiconductor, further, will critically determine the properties of the transistor channel, the glass surface was analyzed in detail. Fig. 2a shows the topography of this glass surface in between the ITO source and drain contacts as revealed by atomic force microscopy (AFM). The surface is seen to be quite smooth,
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Fig. 1. Side view of the layer structure of the bottom-contact/top-gate FET (a) and corresponding source drain electrode pattern (b) as a scheme and laser-microscopy image (c).
scanning electron microscopy (SEM). A continuous film, widely free of pinholes was formed with grain size and morphology widely uniform on the whole surface, indicating good film quality. In the next step of device preparation, a solution of PVA was spun onto the F16PcCu semiconductor film at 1000 rpm for 30 s and cured at 90 °C for 12 h, resulting in a 900 nm thick film. Subsequently, a solution of PVP was used for spin-coating at 1000 rpm for 30 s. The samples were then heated to 120 °C on a hot plate and cured at 200 °C for 20 min. The film thickness of PVP was measured to be 500 nm. The addition of the cross-linking agent PMCF to the PVP solution is advantageous for preparing thin films because the formation of holes in the surface is minimized in cross-linked films [25]. To further avoid leakage currents through the insulator, we used rather thick insulating layers of up to 1.4 mm. To complete the device, the PEDOT:PSS-solution containing Brij C10 was spun on at 3000 rpm for 30 s and cured at 100 °C for 10 s to dry the film and to remove the remaining solvent, leading to a layer of 150 nm thickness and a sheet resistance of 1.5 kΩ cm 1. Brij C10 was added to the aqueous PEDOT:PSS solution to increase wetting and, hence, adherence of the film to the hydrophobic PVP surface. Fig. 3a shows the electrical characteristics of a successfully prepared OFET with a channel width of 10 mm and length of 3 cm. A field-effect mobility of 1.5 10 6 cm2 V 1 s 1was determined for the F16PcCu semiconductor in the channel. A working transistor was achieved at, however, an on/off ratio of only 12. Other FETs of the same structure but with a channel width of 40 mm and a length of 6 cm prepared in this study showed similar on/off at, however, improved mobility values of up to 6.6 10 4 cm2 V 1 s 1. The corresponding characteristics are shown in Fig. 3c. The mobility determined in the present devices fits well to those determined earlier for films of F16PcCu which were prepared
Fig. 2. Atomic force microscopy image of the glass surface after etching off ITO (a) with height range as indicated in the figure and scanning electron microscopy image of the F16PcCu layer deposited into the transistor channel (b).
with some grains of about 13 nm height. This surface served as substrate to grow the semiconducting channel of F16PcCu. Fig. 2b shows the structure of a 30 nm thin film of the semiconductor F16PcCu in the transistor channel as revealed by
Fig. 3. Electrical characteristics (a, c) and photograph (b) of finished bottom-contact/top-gate FETs.
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Fig. 4. Side view of the layer structure of the top-contact/bottom gate FET (a), corresponding source drain electrode pattern with contact pads (b) and laser-microscopy image of the processed electrodes and transistor channel (c).
by the same method, but on the oxidized surface of a silicon wafer [26], which gave values for the electron mobility around 1 10 3 cm2 V 1 s 1. The thickness of the gate insulator in these studies was 300 nm, so in direct comparison, the field-effect is higher and as expected, leads to on/off ratios around 104. A photograph of a complete OFET in our bottom-contact/topgate geometry can be seen in Fig. 3b. Good optical transparency is already noted by eye and a transmittance between 70 and 80 percent was measured by spectrometry in the visible range. The brown tint is caused by the PVA film, which changed color during the thermal treatment, used for curing of the PVP layer. 3.2. Top-contact/bottom gate FET
Fig. 5. Atomic force microscopy images of the PVP-surface (a) below the F16PcCu film (b) in the transistor channel of the top-contact/bottom gate OFET.
Fig. 4a shows a schematic representation of the top-contact/ bottom-gate FETs prepared in this study. As intended, the semiconductor layer is prepared on top of the structure, for example enabling its use for sensing purposes. Further, the addition of the semiconductor layer represents the last step of device preparation avoiding any possible contamination or process damage to the semiconductor film which often consists of quite sensitive materials. The bilayer insulator substrate, furthermore, has the advantage of easy adaptability to other adjacent materials, should the need arise, by either providing a hydrophilic or hydrophobic surface in regards to specific layer designs. The ITO-covered glass substrates were etched to leave a 4 mm wide strip of ITO as gate electrode. A PVA-solution was spun on at 2000 rpm for 30 s and the film was cured at 120 °C for five minutes leaving 150 nm thick PVA. The PVP-solution was spun on at 2000 rpm for 30 s heated to 120 °C and then cured at 200 °C for five minutes, resulting in 350 nm thick PVP. This change in preparation protocol compared to the 20 min curing for the bottomcontact/top-gate TFT led to a dielectric without a colored tint and still sufficiently stable to the subsequent process steps. A negative of the desired source and drain pattern, as seen in Fig. 4b, was developed via photolithography. A microscopic image of the resulting transistor channel is shown in Fig. 4c. The edges of the PEDOT:PSS electrodes are even and the channel width is 55 mm. The substrates were then exposed to a UV/ozone treatment for five minutes in order to allow good adhesion of PEDOT:PSS. To make sure the PVP-surface is suitable to the growth of a compact semiconducting layer of good quality, the surface topography was analyzed by AFM. Fig. 5a shows a PVP-surface
following photolithography and UV/ozone treatment. The surface was measured to be quite homogeneous and flat, except a few grains of about 10 nm height. Since grains of a similar size were seen in Fig. 2a, the glass surface following photolithography and etching, these might consist of remaining photoresist. The PVP surface shows no features of any higher roughness than the glass surface. It is seen that the present preparation steps provide a process which is suitable to prepare structures with sufficient homogeneity to provide appropriate interfaces between insulator and semiconductor. PEDOT:PSS from the solution containing P123 was spun on at 3000 rpm for 30 s and immediately dried at 100 °C for 10 min, leading to a 150 nm thick film. The remaining photoresist was removed in a lift-off using acetone. The substrates were transferred to vacuum where the organic semiconductor F16PcCu was deposited at an average film thickness of 20 nm in the final preparation step. The devices were left in vacuum at room temperature for three days in order to condition the semiconductor towards higher film quality and improved performance as indicated in previous work [26]. The quality of the semiconductor layer was also investigated by atomic force microscopy, shown in Fig. 5b. As seen on glass before (Fig. 2b), film growth occurred in a very uniform way also on this polymer substrate. The surface showed height fluctuations of only up to 10 nm, less than the average film thickness of 20 nm. The grains are uniform in size and shape and form a continuous film without pinholes or obvious discontinuities, providing a semiconductor suitable for OFET with good conduction pathways as also obtained in earlier studies which showed a similar morphology of F16PcCu thin films [26].
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[2]
[3] [4]
[5]
[6] [7]
[8] Fig. 6. Output characteristics of a finished top-contact/bottom gate FET directly after deposition of F16PcCu (a). A photograph of the device is shown as inset (b).
The output characteristics of a device prepared in top-contact/ bottom gate OFET geometry directly after deposition of F16PcCu are shown in Fig. 6a providing a field-effect mobility of 1.5 10 4 cm2 V 1 s 1 and an on/off ratio of 22. These values are quite similar to the values measured for the bottom-contact/topgate devices despite a larger grain size and, hence, less grain boundaries which should lead to improved properties in the topcontact/bottom-gate structure. This effect, however, might be compensated by the influence of the interface area of the semiconductor and the dielectric material. An increased density of electron traps is detrimental to the carrier transport and, thus, can be the cause of the lower mobility we observed. A photograph of the device prepared in top-contact/bottomgate geometry is shown as an inset of Fig. 6a. Optical transparency as observed by eye was measured between 70% and 85%, similar to the values for the devices in bottom-contact/top-gate geometry shown above. The brown tint present in the latter geometry could be avoided by a shorter curing time.
[9]
[10]
[11]
[12]
[13]
[14]
[15]
[16]
[17]
4. Conclusions In conclusion, we have presented strategies to prepare almost ideally transparent organic field-effect transistors using low temperatures and yielding functional microelectronics, demonstrated here for devices in either bottom-contact/top-gate or top-contact/ bottom-gate geometry. The processes established here on ITOcoated glass are well compatible with the use of mechanically flexible ITO-coated polymer substrates, e.g., ITO on PET. The two complementary layering approaches open up a wide range of application possibilities. By the combination of hydrophilic and hydrophobic insulating materials, a range of semiconducting materials and/or contact materials can be chosen. It was shown that the different thin films can be prepared with good quality in the different sequences. Furthermore, it was shown that PEDOT:PSS can be patterned by photolithography on top of a PVP-layer which may be of relevance to the preparation of a variety of organic transparent electronic devices, also beyond the field of OFET.
[18] [19]
[20]
[21] [22]
[23] [24]
[25]
[26]
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