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TTL Logic
Appendix A: TTL Logic A.1 Introduction TTL logic [58] is based on bipolar transistors. TTL is less common today but the comparison to CMOS helps to underline why we need to adhere to certain specifications. Many different logic families have been created with different advantages and design characteristics.
A.2 TTL Logic Circuits Fig. A.1 shows two types of bipolar transistors: NPN and PNP. The three terminals are known as the base, emitter, and collector. The base terminal of the bipolar transistor has a relatively low impedance, in contrast to the high gate impedance of the MOSFET used in CMOS logic. Fig. A.2 shows the characteristic curve plot for an npn bipolar transistor. The plot shows the collector current as a function of emitter-collector voltage for a range of base currents. A minimum level of base current is required to turn on the transistor. Once the transistor is on, the collector current becomes largely a function of the base current. We will discuss bipolar transistor characteristics in more detail in Chapter 4. Fig. A.3 shows a TTL inverter. We can understand its operation for two cases: •
•
When the input voltage is low, Q1 turns on. It creates a flow of current out of Q2’s base. As a result, Q2 is off. Current flows through R2 to turn on Q3, which pulls the output high. The output diode prevents reverse currents through the output stage. If the input voltage is high, current flows through Q1’s emitter to turn on Q2. The current through R3 provides a base-collector voltage to turn on Q4, which pulls the output down.
The Q3, Q4 pair are known as a totem pole output circuit. The TTL fanout problem is caused by limited current. Let’s concentrate here on the case in which the driver transistor’s output is a logic 1. A TTL gate can provide a maximum output current. It also requires a minimum input current. As we add more gates to the fanout, we divide the output current among more sinks. Eventually, none of the sink gates receive enough current to allow them to generate their correct outputs. In this case, the TTL circuit never produces the 187
Appendix A: TTL Logic
Fig. A.1 Bipolar transistors.
Fig. A.2 Characteristic curves for a bipolar transistor.
188
Appendix A: TTL Logic
Fig. A.3 A TTL inverter. VCC VIH VIL VOH VOL IIH IIL
4.5 V £ VCC £ 5.5 V 2.0 V 0.8 V 2.7 V 0.25 V 0.1 mA –0.4 mA
Fig. A.4 Specifications for a TTL logic gate [38].
proper value; in contrast, the CMOS gates will eventually produce a valid output if we give them enough time. Fig. A.4 gives specifications for a TTL logic gate, in this case a 74-series low-power Schottky gate. TTL logic is more sensitive to power supply voltage and the allowable range here is smaller than that for the CMOS gate. While the CMOS logic levels were fairly symmetric, the TTL logic levels are not, with the logic 1 voltage range much larger than the logic 0 voltage range.
A.3 High-Impedance and Open Outputs In the case of TTL, a high impedance configuration is known as open collector. The maximum current supplied by the pullup resistor must be no larger than the maximum sink current of one gate and the current flowing from the inputs of the n fanout gates [58]: 189
Appendix A: TTL Logic RL
VCC VOL, max IOL nIIL
(A.1)
A.4 Example: Open-Collector and High-Impedance Busses Busses are common connections that are used for data communication between various combinations of devices. Only one device at a time may write the bus. The destination for the data may be one or several devices. We can use two different circuit families to design busses with different characteristics. We can use pullup resistors to build busses that allow easy connection and disconnection of devices. If the transistors used on the bus are bipolar, we refer to the bus as open-collector. A classic example of the open-collector bus is I2C, which we discussed in Section 2.3. Fig. A.5 shows an open-collector bus circuit. The bus is a wire connected to pullup resistor Rpu. Each module on the bus has a pulldown transistor Q1, Q2, etc. If any of the devices turns on its pulldown transistor, the bus voltage is pulled to a low voltage. If no modules are on, the bus is kept at a high voltage thanks to the pullup resistor. If two modules turn on their pulldown transistors, the bus continues to operate normally. Open-collector and open-drain busses are robust because they are insensitive to multiple devices writing on the bus. However, the pullup transistor causes the bus to be relatively slow. Fig. A.6 shows a high-impedance bus. Consider first a bus that is only a wire without a pullup resistor. Each module uses a three-state gate to connect to the bus. (We use inverting gates here but the polarity of the bus logic is not important to its circuit characteristics.) If one three-state gate is enabled, it controls the value on the bus. If two three-state gates are enabled and they output the same value, the bus continues to operate. If the two gates have opposite values, they will fight each other, resulting in at least a bad logic value on the bus and perhaps damage to the circuits. If no three-state gate is enabled, the bus is floating and does not have a reliable digital
Fig. A.5 An open-collector bus.
190
Appendix A: TTL Logic
Fig. A.6 A high-impedance bus.
value. We can use a weak pullup to keep the bus at a valid logic value; the pullup is chosen to provide a small enough current that if a three-state gate can overcome it and determine the bus value.
Questions QA.1 A TTL gate has a maximum output current of 16 mA and maximum input current of 1.6 mA. What is the maximum fanout of this gate when it drives other gates of the same type? QA.2 A bipolar family has a maximum output current of 1.6 mA and minimum input current of 40 μA. What is the maximum fanout?
191
A.2 TTL Logic Circuits Fig. A.1 shows two types of bipolar transistors: NPN and PNP. The three terminals are known as the base, emitter, and collector. The base terminal of the bipolar transistor has a relatively low impedance, in contrast to the high gate impedance of the MOSFET used in CMOS logic. Fig. A.2 shows the characteristic curve plot for an npn bipolar transistor. The plot shows the collector current as a function of emitter-collector voltage for a range of base currents. A minimum level of base current is required to turn on the transistor. Once the transistor is on, the collector current becomes largely a function of the base current. We will discuss bipolar transistor characteristics in more detail in Chapter 4. Fig. A.3 shows a TTL inverter. We can understand its operation for two cases: •
•
When the input voltage is low, Q1 turns on. It creates a flow of current out of Q2’s base. As a result, Q2 is off. Current flows through R2 to turn on Q3, which pulls the output high. The output diode prevents reverse currents through the output stage. If the input voltage is high, current flows through Q1’s emitter to turn on Q2. The current through R3 provides a base-collector voltage to turn on Q4, which pulls the output down.
The Q3, Q4 pair are known as a totem pole output circuit. The TTL fanout problem is caused by limited current. Let’s concentrate here on the case in which the driver transistor’s output is a logic 1. A TTL gate can provide a maximum output current. It also requires a minimum input current. As we add more gates to the fanout, we divide the output current among more sinks. Eventually, none of the sink gates receive enough current to allow them to generate their correct outputs. In this case, the TTL circuit never produces the 187
Appendix A: TTL Logic
Fig. A.1 Bipolar transistors.
Fig. A.2 Characteristic curves for a bipolar transistor.
188
Appendix A: TTL Logic
Fig. A.3 A TTL inverter. VCC VIH VIL VOH VOL IIH IIL
4.5 V £ VCC £ 5.5 V 2.0 V 0.8 V 2.7 V 0.25 V 0.1 mA –0.4 mA
Fig. A.4 Specifications for a TTL logic gate [38].
proper value; in contrast, the CMOS gates will eventually produce a valid output if we give them enough time. Fig. A.4 gives specifications for a TTL logic gate, in this case a 74-series low-power Schottky gate. TTL logic is more sensitive to power supply voltage and the allowable range here is smaller than that for the CMOS gate. While the CMOS logic levels were fairly symmetric, the TTL logic levels are not, with the logic 1 voltage range much larger than the logic 0 voltage range.
A.3 High-Impedance and Open Outputs In the case of TTL, a high impedance configuration is known as open collector. The maximum current supplied by the pullup resistor must be no larger than the maximum sink current of one gate and the current flowing from the inputs of the n fanout gates [58]: 189
Appendix A: TTL Logic RL
VCC VOL, max IOL nIIL
(A.1)
A.4 Example: Open-Collector and High-Impedance Busses Busses are common connections that are used for data communication between various combinations of devices. Only one device at a time may write the bus. The destination for the data may be one or several devices. We can use two different circuit families to design busses with different characteristics. We can use pullup resistors to build busses that allow easy connection and disconnection of devices. If the transistors used on the bus are bipolar, we refer to the bus as open-collector. A classic example of the open-collector bus is I2C, which we discussed in Section 2.3. Fig. A.5 shows an open-collector bus circuit. The bus is a wire connected to pullup resistor Rpu. Each module on the bus has a pulldown transistor Q1, Q2, etc. If any of the devices turns on its pulldown transistor, the bus voltage is pulled to a low voltage. If no modules are on, the bus is kept at a high voltage thanks to the pullup resistor. If two modules turn on their pulldown transistors, the bus continues to operate normally. Open-collector and open-drain busses are robust because they are insensitive to multiple devices writing on the bus. However, the pullup transistor causes the bus to be relatively slow. Fig. A.6 shows a high-impedance bus. Consider first a bus that is only a wire without a pullup resistor. Each module uses a three-state gate to connect to the bus. (We use inverting gates here but the polarity of the bus logic is not important to its circuit characteristics.) If one three-state gate is enabled, it controls the value on the bus. If two three-state gates are enabled and they output the same value, the bus continues to operate. If the two gates have opposite values, they will fight each other, resulting in at least a bad logic value on the bus and perhaps damage to the circuits. If no three-state gate is enabled, the bus is floating and does not have a reliable digital
Fig. A.5 An open-collector bus.
190
Appendix A: TTL Logic
Fig. A.6 A high-impedance bus.
value. We can use a weak pullup to keep the bus at a valid logic value; the pullup is chosen to provide a small enough current that if a three-state gate can overcome it and determine the bus value.
Questions QA.1 A TTL gate has a maximum output current of 16 mA and maximum input current of 1.6 mA. What is the maximum fanout of this gate when it drives other gates of the same type? QA.2 A bipolar family has a maximum output current of 1.6 mA and minimum input current of 40 μA. What is the maximum fanout?
191