s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS

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A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS Yuhua Liang, Zhangming Zhu n, Ruixue Ding School of Microelectronics, Xidian University, Xi’an 710071, China

art ic l e i nf o

a b s t r a c t

Article history: Received 24 October 2014 Received in revised form 11 March 2015 Accepted 21 August 2015

A 10-bit 300-MS/s asynchronous SAR ADC in 65 nm CMOS is presented in this paper. To achieve low power, binary-weighed capacitive DAC is employed without any digital correction or calibration. Consequently, settling time for the capacitive DAC would be a dominant limiting factor for the ADC operating speed. A novel architecture is proposed to optimize the settling time for the capacitive DAC, which depends merely on the on-resistance of switches and the capacitance of unit capacitor and irrelevant to the resolution. Therefore, high-speed high-resolution SAR ADC is possible. What is deserved to highlight is that the architecture improves the ADC performance at a fraction of the cost, with only some capacitors and control logic added. Post-layout simulation has been made for the SAR ADC. At a 1.2-V supply voltage and a sampling rate of 300 MS/s, it consumes 1.27 mW and achieves an SNDR of 60 dB, an SFDR of 67.5 dB, with the Nyquist input. The SAR ADC occupies a core area of 450
380 μm2. & 2015 Elsevier Ltd. All rights reserved.

Keywords: SAR ADC Low power High speed Settling time Asynchronous

1. Introduction With the feature size of CMOS devices scaled down, SAR ADC is going mainstream as the feature size of CMOS devices scales down. Its distinctive characteristics are simple structure, high energy-efficiency and outstanding compatibility with the digital process. SAR ADC, requiring several comparison cycles to complete one conversion, generally has limited operational speed. In recent years, many experts are dedicating to improving the operational speed for SAR ADC [1–4]. Time-interleaved SAR ADC proposed in [1] requires harsh clock accuracy since Signal-to-noise ratio (SNR) is destructible by clock jitter. Flash-SAR ADC proposed in [2] would introduce static power due to flash ADC. Resistors, of which the mismatch property is poorer, are also used in this architecture. In addition, more than one comparator is employed. Since offset still exists among the comparator offset voltages, offset canceling for the comparator would be of the essence. Pipeline-SAR ADC proposed in [3,4] can realize both high-speed and relatively low-power specifications by reducing the number of opamps. Nevertheless, the requirement of interstage gain in the architecture still requires at least one op-amp. This will not only consume static power, but also set limitations to compatibility with system-onchip (SOC) under low supply voltage condition. With this proposed strategy, the settling time of the DAC can be reduced significantly to improve the operation speed, while only SAR ADC topology and one n

Corresponding author. Tel.: þ 86 29 88202562; fax: þ86 29 88202562. E-mail address: [email protected] (Z. Zhu).

comparator are required. Moreover, the settling time is insensitive to the resolution, making possible the high-speed high-precision SAR. Employed the proposed architecture, a 1.2-V 10-bit 300-MS/s SAR ADC is designed in 65 nm CMOS technology. Post-layout simulation shows that at a 300 MS/s sampling rate, the ADC achieves an ENOB of 9.67 bits and consumes 1.27 mW with the Nyquist input, resulting in a FOM of 5.2 fJ/conversion-step.

2. Architecture design Since the SAR search algorithm resolves a single bit on each clock cycle, it is difficult to simultaneously increase both resolution and throughput. During one conversion, most of the time is occupied by DAC settling time, comparator decision time and reset time. With the circuit structure described in [5], the comparator decision time and reset time can reach 100 ps and 80 ps, respectively. Consequently, DAC settling time becomes the major limiting factor. In this paper, a novel strategy to improve the settling time is proposed. To illustrate the proposed strategy, case of 4-bit resolution is taken as an example. As shown in Fig. 1, the whole DAC is comprised of three sub-DACs. The most significant two bits are obtained by Sub-DAC1, while the other sub-DACs contribute to only one bit. Top-plates sampling is employed to save half the capacitors. In the sampling phase, switches ST are closed and input signals, VIP and VIN, are sampled on the top-plates of capacitors. All the bottom-plates of capacitors are initially loaded with the

http://dx.doi.org/10.1016/j.mejo.2015.08.008 0026-2692/& 2015 Elsevier Ltd. All rights reserved.

Please cite this article as: Y. Liang, et al., A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.08.008i

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2

P0

Sub-DAC1 c

ST

VIP

ST

c

S1

+

S1

-

VIN

c

c

N0

Sub-DAC2 VIP

c

ST

P1

P0

c

2c

S2

+

S2

ST

-

VIN c

c

2c

N1

N0

P1

P0

Vp

VOP

tDAC = Tcomp − tcomp − tdelay Vn

VON

Sub-DAC3 P2 VIP

ST

c

c

2c

4c

-

VIN c

c

2c

4c

N2

N1

N0

t

0. 99Vfinal = Vfinal (1 − e− τ )

S3

Sample

(2)

The required settling time t can be calculated from (2) to be 4.6τ. As a consequence, the following formulas must be satisfied, so that the settling for each capacitor can be guaranteed.

Fig. 1. Proposed topology for 4-bit SAR ADC.

Sample rate clock

(1)

If a switch (on-resistance equals Ron) connects the corresponding capacitor (capacitance equals C) from ‘0’ to ‘1’, the time required for the voltage across the capacitor to settle sufficiently to 99% of the final value can be calculated from the following expression, where Vfinal represents the final value across the capacitor, and τ is equal to Ron times C.

S3

+

ST

before the third rising edge of comparator coming. With regard to the following comparisons, operations are done similarly. Assuming the on-resistance of switches connecting bottomplates of capacitors to either ‘0’ or’1’ to be Ron, time-constants for each capacitor in the sub-DACs are listed in Table 1. Architecture for the proposed SAR with resolution being 4-bit is shown in Fig.3. The decision time for comparator is represented by tcomp and the delay time from comparator outputs to DAC is represented by tdelay. Let the period of comparator clock be Tcomp, the maximum settling time for DAC within each comparison cycle can be expressed as:

Conversion

Comparator clock ST

⎧ 4. 6 × τ13 ≤ tDAC ⎪ 4. 6 × τ 22 ≤ tDAC ⎪ ⎪ 4. 6 × τ 31 ≤ tDAC ⎪ ⎨ 4. 6 × τ 23 ≤ Tcomp + tDAC ⎪ ⎪ 4. 6 × τ ≤ T 32 comp + tDAC ⎪ ⎪ ⎩ 4. 6 × τ 33 ≤ 2Tcomp + tDAC Substituting data in Table 1 into (3), (3) can be rewritten as

S1 S2 S3

Fig. 2. Switching scheme for ST, S1, S2, S3 and comparator clock.

sequence of ‘0000’. Subsequently, the comparison phase arrives. Switching sequences for ST, S1, S2, and S3 are shown in Fig. 2, and comparator clock is generated by asynchronous control logic to achieve high speed goal. On arrival of the falling edge of the sample rate clock, ST, S2, and S3 are switched off, and only S1 is still on. In a situation like this, no sub-DACs except for sub-DAC1 is connected to comparator for conversion. On account of top-plates sampling, the MSB can be obtained the moment the first rising edge of the comparator clock arrives, with no capacitor switched. According to the MSB, either P0 or N0, would be switched from ‘0’ to ‘1’. For example, if MSB¼0, all switches P0 belonging to subDAC1, sub-DAC2, sub-DAC3 would be switched from ‘0’ to ‘1’. Then voltages across capacitors in all sub-DACs begin to re-established, but only settling of sub-DAC1 influences the second bit, which is obtained once the second rising edge of the comparator clock arrives. Since in sub-DAC1, the switched capacitor for the second bit is equal to unit capacitor, the course of settling can be completed soon. After the second comparison, clk1 is activated, so that S1 is turned off and S2 is closed to connect sub-DAC2 to the comparator. Meanwhile, according to the refreshed comparator result, P1 or N1 would be switched in the similar way. Note that there should be enough time for the voltage across capacitors in sub-DAC2, resulting from both P0/N0 and P1/N1, to establish well

(3)

⎧ 1 4. 6 × R on C ≤ tDAC ⎪ 2 ⎪ ⎪ 3 4. 6 × R on C ≤ tDAC ⎪ 4 ⎪ 7 ⎪ 4. 6 × R on C ≤ tDAC ⎨ 8 ⎪ ⎪ 4. 6 × R on C ≤ Tcomp + tDAC ⎪ ⎪ 4. 6 × 3 R C ≤ T on comp + tDAC ⎪ 2 ⎪ ⎩ 4. 6 × 2R on C ≤ 2Tcomp + tDAC

(4)

Since tDAC < Tcomp holds true, which can be deduced according to (1), one can found that (4) can be simplified just by the inequality relevant to τ 31. That is:

4. 6 ×

7 R on C ≤ tDAC 8

(5)

Tcomp, tdelay and tDAC can be adjusted by the logic delay, separately, while tcomp is approximately 200 ps, as is mentioned above. By this analogy, the conclusion for N-bit resolution can be drawn in the similar way. The only restriction for settling occurs when the LSB Table 1 Time-constant relevant to each capacitor for 4-bit SAR ADC. τ

P2/N2

P1/N1

P0/N0

Sub-DAC1 Sub-DAC2 Sub-DAC3



τ31 ¼ 7/8RonC


τ 22 = 3/4RonC τ32 ¼ 3/2RonC

τ13 ¼1/2 RonC τ23 ¼ RonC τ33 ¼ 2RonC

Please cite this article as: Y. Liang, et al., A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.08.008i

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Inputs

S1 Vip Vin

Vip Vin

S2

Voutp

S3

Vp

DAC

S1 S2 S3

Vn

Voutn

P0 P1 P2 N0 N1 N2

Register

tcomp tdealy

b0 P0 P1 P2 N0 N 1 N2 Voutp b1 SAR b2 Voutn b3 clk1 clk2 clk3

Decoder

bootstrapped

Sample

3

clk1 clk2 clk3

Fig. 3. Proposed SAR ADC architecture with resolution being 4-bit.

capacitor in sub-DAC(N 1) is switched. It can be deduced as follows:

tDAC ≥ 4. 6 ×

2N − 1 − 1 R on C ≈ 4. 6 × R on C 2N − 1

(6)

It can be seen from formula (6) that the settling time tDAC is independent of the resolution N. Assume that pulse width of sample signal PW¼500 ps, Ron ¼200 Ω , C¼20 fF, and tdelay ¼ 100 ps, estimation with bit of conservative, a simulation on the operation speeds with the proposed strategy is shown in Fig. 4. Need of special note is that the operation speed with the proposed strategy is improved at the expense of using 2× capacitors, compared with the traditional method consisting of only one capacitor array. Therefore, 2 × chip area is required. However, under certain application conditions, it is not necessary to take the architecture consisting of (N 1) sub-DACs. For example, if the resolution is 10-bit, and the operation speed is desired to be 300 MHz, 2 or 3 sub-DACs might be sufficient. In this way, a tradeoff can be undertaken between chip area and the speed specification.

3. Circuit implementation Schematics of S/H, high speed dynamic comparator, capacitive DAC consisting of several sub-DACs and asynchronous control logic are listed and discussed detailedly in this section. 3.1. S/H Circuit The non-ideal effects of S/H circuit consist mainly of thermal noise, finite sampling bandwidth, non-linear distortion relevant to the signal, charge injection, clock jitter and clock feed-through. For high speed case, non-linear distortion relevant to the signal and finite sampling bandwidth would be major limitations. Assume that the settling error Verr is required to be less than half of LSB and pulse width of SAMPLE is PWs, on-resistance of the bootstrapped switch Ron can be derived as follows in the worst case that the input signal leaps from 0 to the full scale.

R on ≤

PWs Ctotal·(N + 1)·ln 2

(7)

where Ctotal, representing the total capacitance of the sampling capacitor, equals to the sum of capacitance for each capacitor in the DAC array here. In this work, N is 10-bit, capacitance of unit capacitor is 8 fF. Consequently, Ctotal is equal to 4.2 pF. PWs is set to 300 ps, leading to a maximum on-resistance of 9.6 Ω for Ron .

Fig. 4. Operation speeds SAR can achieve with the proposed strategy.

The switches are turned off once the gate voltage of the switches decreases below (VIN þ VTHN). Therefore, the time point of turning off is closely related to the signal. This will introduce harmonic and worsen the THD performance. According to [6,7], the third harmonic expressed as below could be generated

HD3 ≈

⎞2 3⎛ A ⎜ 2πfIN Tf ⎟ 8 ⎝ Vgate_H ⎠

(8)

where A and fIN are the signal amplitude and frequency, respectively. Tf represents the fall time of the gate voltage. Vgate_H stands for the high gate voltage of the switch. The maximum Signal-toDistortion-Ratio (SDR) is [6,7]

SDRMAX = 20 log

Vgate_H −4 AfIN Tf

(9)

It can be seen from (9) that Tf should be small enough to improve SDRMAX . Schematic of the bootstrapped switch in this work is shown in Fig. 5. Current paths, path1 and path2, are added to the conventional architecture. Path1 plays the role of accelerating the switchingon action to guarantee the sampling accuracy, while path2 speeds up the switching-off action to suppress harmonics. 3.2. Comparator High-speed low-noise comparator is an essential functional block for high-speed SAR ADC. Thermal noise is always in the form of kT/C. Since capacitors in the capacitive DAC serves as the

Please cite this article as: Y. Liang, et al., A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.08.008i

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4

SAMPLE

SAMPLE_B

path1 SAMPLE_B

boost

SAMPLE

SAMPLE_B

path2

VOUT1 SAMPLE

VIN

VOUT2

Fig. 5. Schematic of the bootstrapped switch.

Fig. 6. Schematic of the high-speed dynamic latch comparator.

sampling capacitor together and Ctotal is equal to 4.2 pF, thermal noise from outputs of the bootstrapped would be as low as 31 μV/ √Hz and deserve no particular consideration. With respect to the input-referred noise of the comparator, the post-layout extraction indicates that load capacitor at the comparator output is 12.2 fF. Therefore, the thermal noise at the comparator output is 0.58 mV/ √Hz. Since top-plate sampling is employed in this design, one LSB of the proposed SAR ADC turns out to be 2.34 mV ( ¼FS/29). Note that the thermal noise at the comparator output is only 0.25 LSB, and is in the same order as the quantization noise of the ADC. According to the analysis presented in [8,9], the delay time of the comparator ttotal can be divided into two parts: t0 (phase 1) and tlatch (phase 2), which can be expressed as

CL × Vthp t0 = Iinput − pairs

tlatch =

⎛ ∆V ⎞ CL ln ⎜ 2 out ⎟ ⎝ G m.eff Vo ⎠

(10)

(11)

where CL represents the capacitive load at the output node, Iinput − pairs is the discharge current flowing through the input transistors during phase 1, Vo is the initial voltage difference at the input nodes of the inverters in phase 2, Gm.eff is the transconductance of the inverters. In this work, a comparator based on [5] is designed as shown in Fig. 6. During the amplification phase (COMP_start¼‘0’), M3 is turned on and M1–M5 comprise a differential amplifier, with the on-resistance of M4 and M5 being the resistive load. In this way, the difference voltage at the input nodes is amplified and fed to the regenerative latch stage. Voltage at input node of each inverter is approximately VDD − Vthp , rather than VDD. In this way, the delay time t0 can be

reduced significantly. During the regenerative phase (COMP_ start¼‘1’), M3 is off to prohibit the operation of the amplifier stage while M10 is turned on to enabling the regenerative stage. Subsequently, the comparison result would be generated at VOP and VON nodes. Since gain of the amplifier stage is larger than one, tlatch would also be reduced to some extent. Simulation result shows that the comparison time and the reset time of this comparator can reach as fast as 100 ps and 80 ps, respectively. 3.3. Capacitive DAC If the two-subDAC architecture as shown in Fig. 7 is adopted, an analysis similar to that in the previous section can be made as below

⎧ 4. 6 × 4R on C ≤ tDAC ⎪ 496 × 16 ⎪ 4. 6 × R on C ≤ 5Tcomp + tDAC ⎪ 512 ⎪ ⎪ 4. 6 × 480 × 32 R on C ≤ 6Tcomp + tDAC ⎪ 512 ⎪ ⎨ 448 × 64 R on C ≤ 7Tcomp + tDAC ⎪ 4. 6 × 512 ⎪ ⎪ 384 × 128 R on C ≤ 8Tcomp + tDAC ⎪ 4. 6 × 512 ⎪ ⎪ 256 × 256 R on C ≤ 9Tcomp + tDAC 4. 6 × ⎪ ⎩ 512

(12)

To reduce the delay time tdelay, the bottom plates of the capacitors are all initially connected to ‘0’ so that the comparator outputs VOP and VON can control the switches without being decoded. Setting the sampling time to be 300 ps within each conversion circle, the period

Please cite this article as: Y. Liang, et al., A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.08.008i

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Fig. 7. Schematic of the capacitive DAC consisting of two sub-DACs.

CLK

CLK SAMPLE

RDY

CLK

bit-slice

Valid

bit-slice

CLK

SAMPLE

bit-slice

VOP VON RDY

COMP_start

D VOP

D

VON N

CLK

CLK

Q

RDY

P SAMPLE

Fig. 8. Schematic of asynchronous logic based on the bit-slice cell. (a) Schematic of overall asynchronous logic. (b) Schematic of bit-slice cell. (c) Schematic of RDY.

of comparator clock Tcomp would be 300 ps for 300 MS/s-sampling rate and 10-bit resolution. The delay time tdelay in this design is approximately 60 ps. On condition of leaving a margin of 40 ps within each comparison cycle to overcome the PVT variation for asynchronous logic, the remaining time for DAC settling in each comparison cycle would be 100 ps. Based on the above time-distribution strategy, (10) can be simplified to

4. 6 × 128R on C ≤ 9Tcomp + tDAC

(13)

(13) indicates that the maximal settling time of this architecture is relaxed by 9Tcomp when compared to that of the conventional architecture.

In this design, unit capacitor is set to approximately 8 fF to satisfy the matching requirement. Hence, the on-resistance of the switch should be no more than 600 Ω . 3.4. Asynchronous logic Schematic of the asynchronous control logic in this design is shown in Fig. 8(a). To deal with the circuit complexity and reduce the delay time tdelay, the bit-slice cell [10] shown in Fig. 9(b) is employed. RDY block described in Fig. 8(c) executes the functionality of judging whether one conversion is completed. It can be seen from Fig. 8 that the control logic has been designed to be as simple as possible, so that the delay time between the logic

Please cite this article as: Y. Liang, et al., A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.08.008i

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6

Path 2 Pi

SAMPLE

DAC well settled

Ni

VOP SAMPLE

COMP_start VON Path 1

Valid

COMP_start

VOP/VON reset

Valid

COMP_start

’ RDY’ disable ’ RDY’ enable

Fig. 9. Illustration of the relationship between each signal.

cells can be reduced to the greatest extent. The outputs of the comparator, VOP and VON, are fed to the bit-slice cells without decoding. Meanwhile, the outputs of the bit-slice cells, Pi and Ni (i¼1,2,…,9), are connected to the gates of switching transistors and decide the connecting relationship of the bottom-plates of the capacitors, either to ‘1’ or to ‘0’. The logical relationship between each signal in the control logic is illustrated as in Fig. 9. “Path 1” generates the signals (Pi and Ni) for the switches and defines the settling time for the capacitive DAC in each comparison cycle, while “path 2” produces the periodic signal “COMP_start” to activate the comparator. The “RDY” signal verdicts whether a conversion is finished. “RDY” is initially discharged to ‘0’. When “COMP_start” is reset to ‘1’ in a comparison cycle, it indicates the termination of this comparison cycle. At this time, if “RDY” still maintains low, the next comparison cycle is activated. On the contrary, if “RDY” changes to high, it means that the current conversion is over. Then “SAMPLE” is changed to ‘1’ to sample the signal and enable the next conversion cycle.

Fig. 10. Layout of the proposed SAR ADC.

Breakdown of power consumption Bootstrapped B d switch 4%

Com mparator 9%

CDAC 48%

4. Layout and post-layout simulation results This section shows all simulation results using the extracted netlist of the designed layout, which is shown in Fig.10. An area of 220
320 μm2 is occupied by the core of the proposed SAR ADC in 65 nm 1.2 V 1P6M CMOS process. Compared to the conventional architecture, though only 32 unit capacitors and a few logic cells are added in the proposed architecture, the performance can be improved significantly. Capacitance of the unit capacitor in this work is designed to 8 fF. On the premise of the sampling rate, the proposed SAR ADC consumes 1.27 mW from a 1.2-V supply voltage. Fig. 11 shows the breakdown of simulated power consumption for each block. Capacitance of the unit capacitor in this work is designed to 8 fF. On the premise of the sampling rate, the proposed SAR ADC consumes 1.27 mW from a 1.2-V supply voltage. Fig. 11 shows the breakdown of simulated power consumption for each block. The capacitive DAC and the control logic consume 48% and 39% of the total power, respectively. The differential nonlinearity (DNL) and integral nonlinearity (INL) of the proposed SAR is shown in Fig. 12. It can be seen that the maximum DNL is  0.23/0.37 LSB, while the maximum INL is 0.48/0.32 LSB. An 8192-point fast Fourier transform (FFT) of the 300 MS/s SAR ADC at near–Nyquist operation is shown in Fig. 13. On condition of the amplitude of the input signal is set to  0.5 dBFS, the Signal-to-Noise and Distortion Ratio (SNDR) and the spurious free dynamic range (SFDR) can reach 60 dB and 67.5 dB, respectively. In addition, the power efficiency can achieve high level due to the very simple architecture. The Effective Number of Bits (ENOB) of the proposed SAR ADC is 9.67 bits. To compare the proposed ADC to other works with different sampling rates and resolutions, the figure-of-merit (FOM) is essential. It is defined as below

Logic 39%

Fig. 11. Simulated power breakdown of each block.

FOM =

power min {2 × ERBW, fs } × 2ENOB

(14)

where ERBW represents the effective resolution bandwidth of the converter. Since only 1.27 mW is consumed under the 1.2 V supply voltage, according to (14), the FOM of the proposed ADC is 5.2 fJ/ conversion-step. Fig. 14 exhibits the dynamic performance as the input frequency is swept at 300 MS/s. The ADC achieves a peak SNDR of 61.5 dB. Within the input frequency range (up to the Nyquist frequency), the SNDR decreases by 1.5 dB. Hence, the effective resolution bandwidth (ERBW) of the SAR ADC is higher than the Nyquist bandwidth. 50 times Monte-Carlo simulations are made to evaluate the influence of process variation and mismatch. Detailed occurrence versus each ENOB has been listed in Table 2. As shown in Fig. 15, the mean value and 3 × sigma of the ENOB are 9.66 bits and 0.2 bits, respectively. Therefore, the proposed SAR ADC has a excellent performance. To analyze what are the causes of ENOB fluctuation shown in Fig. 15, simulations on ENOB under different simulation corners are made, on the premise that only process variation exists and no mismatch is taken into consideration. The simulation results listed in Table 3 indicates that ENOBs under different corners are almost equal. Hence, it can be concluded from Table 3 that process variation has very little influence on the ENOB fluctuation. In other words, ENOB

Please cite this article as: Y. Liang, et al., A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.08.008i

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Table 2 Occurrence versus ENOB. ENOB (bits) Occurrence (times)

9.4 1

9.45 2

9.5 4

9.55 6

9.6 6

9.65 7

9.7 8

9.75 5

9.8 6

9.85 5

Fig. 15. Results of 50-times Monte-Carlo simulation.

Table 3 ENOBs under different corners. Fig. 12. Simulated DNL and INL. ENOB (bits)

S

T

F

SS SF TT FS FF

9.645 9.656 9.673 9.651 9.666

9.627 9.634 9.671 9.651 9.658

9.602 6.464 9.670 9.643 9.652

SS, SF, TT, FS and FF in the left column of Table 3 represent the corners of NMOS and PMOS, while S, T, F in the top row represent the corners of the capacitor.

Fig. 13. 8192-point FFT spectrum at 300 MS/s with Nyquist input.

capacitor areas could reduce the mismatch errors, and improve dynamic performance of the ADC to some extent, power consumption will be increased meanwhile. Besides, large capacitor would impose difficulty on the DAC settling, and restrict the operation speed of the ADC. At a speed of 300 MS/s, Monte Carlo simulation result shown in Fig. 15 indicates that the proposed ADC has possessed a stable performance, with the FOM of it improved to 5.2 fJ/conversion-step. Table 4 summaries the performance of the proposed SAR ADC and compares it with other state-of-the-art works [11–14]. The conclusion that each aspect of performance for the proposed ADC, such as circuit complexity, power efficiency, chip area, and working speed, is much superior can be drawn from Table 4.

5. Conclusion

Fig. 14. Dynamic performance of the SAR ADC versus input frequency sampled at 300 MS/s.

fluctuation results mainly from mismatch among capacitors in the DAC. There is a compromise among the dynamic performance, energy efficiency and operation speed of the ADC. Though increasing

A novel architecture aiming at reducing the settling time of the capacitive DACs in SAR ADCs is proposed. With the proposed strategy, only 32 unit capacitors and a few digital cells are added to the conventional architecture. However, both working speed and power efficiency can be improved significantly. A 1.2-V 300Ms/s 10-bit SAR ADC based on the proposed architecture is designed in 65-nm CMOS technology. Post-layout simulation results show that at 300 MS/s sampling rate, the ADC achieves a SNDR of 60 dB and consumes 1.27 mW with the Nyquist input. Consequently, the FOM can be optimized to 5.2 fJ/conversion-step.

Please cite this article as: Y. Liang, et al., A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.08.008i

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Table 4 Comparison with state-of-the-art works.

Technology (nm) Architecture Resolution (bits) Sampling rate (MS/s) Supply voltage (V) SFDR (dB) @Nyquist SNDR (dB) @Nyquist ENOB (bits) @Nyquist Power (mW) FOM (fJ/conv.-step) @ Nyquist

ISCAS’2013 [11]

JSSC’2013 [12]

ISCAS’2014 [13]

ASICON’2011 [14]

This work

65 SAR 8 100 0.6 68 48.8 7.81 0.524 23.35

65 BS-TI SAR 10 170 1 69.1 53.2 8.5 2.3 36.4

65 SAR 10 150 1.2 82.86 60.55 9.77 1.476 11.19

65 SAR 10 100 1 68.367 58.364 9.403 1.609 24

65 SAR 10 300 1.2 67.5 60 9.67 1.27 5.2

Results in [11] and [13] are from pre-layout simulation, [14] is from post-layout simulation, while [12] is measured.

Acknowledgments This work was supported by the National Natural Science Foundation of China (61234002, 61322405, 61306044, 61376033), the National High-tech Program of China (2013AA014103).

References [1] Dusan Stepanovic, Borivoje Nikolic, A 2.8 GS/s 44.6 mW time-interleaved ADC achieving 50.9 db SNDR and 3 db effective resolution bandwidth of 1.5 GHz in 65 nm CMOS, IEEE J. Solid-State Circuits 48 (4) (2013) 971–982. [2] Young-Kyun Cho, Jae-Ho Jung, Kwang Chun Lee, A 9-bit 100 MS/s flash-SAR ADC without track-and-hold circuits, in: Proceedings of IEEE International Symposium On Wireless Communication Systems, ISWCS, 2012, pp. 880–884. [3] C.C. Lee, M.P. Flynn, A 12b 50 MS/s 3.5 mW SAR assisted 2-stage pipeline ADC, in: Proceedings of IEEE International Symposium On VLSI Circuits Digest of Technical Papers, 2013, pp. 239–240. [4] Jayanth Kuppambatti, Peter Kinget, current reference pre-charging techniques for low-power zero-crossing pipeline-SAR ADCs, IEEE J. Solid-State Circuits 49 (3) (2014) 683–694. [5] Mohamed Abbas, Yasuo Furukawa, Satoshi Komatsu, Takahiro J. Yamaguchi, Kunihiro Asada, Clocked comparator for high-speed applications in 65 nm technology, In: Proceedings of IEEE Asian Solid-State Circuit Conference, 2010, pp. 1–4.

[6] W. Yu, S. Sen, B.H. Leung, Distortion analysis of MOS track-and-hold sampling mixers using time-varying volterra series, IEEE Trans. Circuits and Systems II 46 (2) (1999) 101–113. [7] Behazd Razavi, Principles of Data Conversion system Design, Wiley, New York (1995), p. 7–28. [8] Bernhard Wicht, Thomas Nirschl, Doris Schmitt-LandsiedelMoni, High-speed and low-power dynamic latch comparator, IEEE J. Solid-State Circuits 39 (7) (2004) 1148–1158. [9] D. Johns, K. Martin, Analog Integrated Circuit Design, Wiley, New York, 2000. [10] Pieter Harpe, Guido Dolmans, Kathleen Philips, Harmke de Groot, A 0.7 V 7-to-10 bit 0-to-2 MS/s flexible SAR ADC for ultra low-power wireless sensor nodes, In: Proceedings of ESSCIRC, 2012, pp. 373–376. [11] Wen-Lan Wu, Yan Zhu, Li Ding, Chi-Hang Chan, U.-Fat Chio, Sai-Weng Sin, U. Seng-Pan, Rui Paulo Martins, A 0.6 V 8b 100 MS/s SAR ADC with minimized DAC capacitance and switching energy in 65 nm CMOS, In: Proceedings of IEEE International Symposium On Circuits and Systems, ISCAS, 2013, pp. 2239– 2242. [12] Si-Seng, Chio U-Fat, Zhu Yan, Sin Sai-Weng, U. Seng-Pan, Martins Rui Paulo, A 2.3 mW 10-bit 170 MS/s two-step binary-search assisted time-interleaved SAR ADC, IEEE J. Solid-State Circuits 48 (8) (2013) 1783–1794. [13] Xiaoyang Wang, Qiang Li, A 10-bit 150 MS/s SAR ADC with parallel segmented DAC in 65 nm CMOS, In: Proceedings of IEEE International Symposium On Circuits and Systems, ISCAS, 2014, pp. 309–312. [14] Jun Ma, Yawei Guo, Li Li, Yue Wu, Xu Cheng, Xiaoyang Zeng, A low power 10- bit 100 S/s SAR ADC in 65 nm CMOS, In: Proceedings of the IEEE 9th International Conference on ASIC, ASICON, 2011, pp. 484–487.

Please cite this article as: Y. Liang, et al., A 10-bit 300-MS/s asynchronous SAR ADC with strategy of optimizing settling time for capacitive DAC in 65 nm CMOS, Microelectron. J (2015), http://dx.doi.org/10.1016/j.mejo.2015.08.008i