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The effect of gate overlap on the device degradation in IGZO thin film transistors
Microelectronics Reliability 54 (2014) 2167–2170
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
The effect of gate overlap on the device degradation in IGZO thin film transistors Dae Hyun Kim, Jong Tae Park ⇑ Department of Electronics Engineering, Incheon National University, #119 Academi-Ro Yoonsu-Gu, Incheon 406-772, Republic of Korea
a r t i c l e
i n f o
Article history: Received 24 June 2014 Accepted 8 July 2014 Available online 5 August 2014 Keywords: InGaZnO thin film transistor Device reliability Gate overlap
a b s t r a c t The effect of gate overlap on the device degradation in IGZO TFTs treated by H2 and Ar plasma was experimentally investigated after positive and negative gate biases stress and hot carrier stress. Using transmission line method, the effective channel length was extracted with the length of the gate overlaps. After positive and negative biases stress, the decrease of threshold voltage shifts with the increase of the gate overlaps may be attributed to the carrier diffusion from the n extended source and drain regions to the intrinsic channel region. The hot carrier induced threshold voltage shifts were increased with the increase of the gate overlap due to the reduction of effective channel length. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction Amorphous IGZO thin film transistors are attractive candidates for pixel drivers in display applications, such as active-matrix organic light emitting diode, active matrix liquid crystal displays, and flexible display due to their transparency and excellent electrical properties, including high mobility and on/off current ratio. A staggered bottom gate structure of IGZO TFT with an etch stopper layer is widely used for transparent display applications, but it has a high parasitic capacitance and series resistance due to the existence of overlap region between gate and source/drain electrode. In order to overcome these disadvantages, a device structure of source/drain formed by plasma etching process with etch stop layer has been introduced instead of the typical lift-off process [1]. It is known that H2 and Ar plasma treatment can improve the film conductivity by increasing electron concentrations of IGZO film without degradation of mobility [2]. In this process, H+ ion can diffuse into IGZO film and acts as a donor and thus the source/drain regions can be highly doped as n+. It was previously reported that the highly conductive region doped by H+ ions can be extended into the channel region and the effective channel lengths of IGZO TFTs could be defined as like those of lightly doped drain (LDD) MOSFETs [3]. The diffusion of H+ ion from the n+ doped source and drain region to the intrinsic channel region leads to that the short channel devices exhibit a more negative initial threshold voltage compared to the long channel devices [4].
⇑ Corresponding author. Tel.: +82 (32) 835 8445; fax: +82 (32) 835 0774. E-mail address: [email protected] (J.T. Park). http://dx.doi.org/10.1016/j.microrel.2014.07.011 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
In conventional staggered bottom gate structure of TFTs, the highly n+ doped source/drain region and the gate overlap (LOV) lead to the current distributed over a wider contact area and thus reduce the parasitic resistance [5]. With assumption of gradually doped source/drain region, the simulation result showed that the effective channel length was decreased with increase of LOV and VGS [3]. Therefore, LOV influences the device performance and instability. The device instability of IGZO TFTs was intensively studied under both positive and negative gate bias stress [6,7]. And the drain bias induced hot carrier effect on the device degradation was also reported recently [8]. Although the effect of gate overlap lightly doped drain on low temperature poly-Si thin film transistor was addressed [9], there is no profound study on the effect of LOV on the device degradation in IGZO TFTs within our knowledge. In this work, the effect of LOV on the device degradation in IGZO TFT which was treated by H2 and Ar plasma was experimentally investigated after positive and negative gate biases stress and hot carrier stress. The device instabilities of IGZO TFTs were analyzed with the various length of LOV. 2. Device fabrication and measurement Staggered amorphous IGZO thin film transistors with bottom gate were fabricated on a glass substrate, where Mo was deposited as a gate electrode using RF sputtering. A 200 nm thick SiNx layer was deposited as a gate dielectric material by PECVD at 300 °C. An 50 nm thick amorphous IGZO (1:1:1 mol of Ga2O3:In2O3:ZnO) film was deposited by RF sputtering at a deposition power of 100 W, a working pressure of 6 mTorr in an ambient of Ar with a flow rate of 30 sccm. After defining the active IGZO channel region using
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photolithography and wet etching, SiOx was deposited for the etch stop layer and patterned. Then the etch stop layer was etched by a reactive ion etching method with a gas mixture of Ar and CHF3. During this plasma treatment, the source and drain regions of IGZO layer were exposed to Ar and CHF3 and thus supposed to be highly n+ doped region [2]. The LOV ranging from 0 lm to 3 lm is determined by the extension of exposed source and drain regions. A 150 nm thick Mo layer was deposited and patterned for the source and drain electrodes and then etched by a reactive ion etching. Finally, all devices were annealed in oven at 350 °C for 1 h. Fig. 1 shows the schematic diagram of a fabricated IGZO TFT. The electrical characteristics of the transistors were measured with an Agilent B1500A precision semiconductor parameter analyzer in dark conditions and in air. The gate and/or drain biases were interrupted at fixed times to record the transfer characteristics of the transistor at room temperature. Measurements were made on transistors with a physical gate length (L) ranging from 8 lm to 30 lm and a width (W) ranging from 14 lm to 64 lm.
Fig. 2. Transfer characteristics of IGZO TFTs with L = 25 lm and W = 24 lm for different LOV.
3. Results and discussion 3.1. Electrical characteristics with gate overlaps Fig. 2 shows transfer characteristics of IGZO TFTs with L = 25 lm and W = 24 lm for different LOV. It is remarkable that the transfer curves are shifted negatively and the ON currents are increased slightly as LOV increases. The reason for this interesting observation is believed due to the decrease of the effective channel length (Leff) which is resulted from a highly conductive source and drain regions extended into the intrinsic channel region as previous report [3]. The variation of Leff with the gate overlap will be further discussed. Since the current flows through all contact area under the highly doped source and drain electrode in IGZO TFTs, the total source-to-drain resistance of IGZO TFTs operated in the linear region can be generalized as a function of VGS [10].
RTOT ðV GS Þ ¼ RCH ðV GS Þ þ RSD ðV GS Þ
ð1Þ
where RCH is the effective channel resistance that can be expressed by
RCH ðV GS Þ ¼ Leff ðV GS Þ=W lC G ðV GS V TH 0:5V DS Þ
ð2Þ
RSD is all the resistance outside the channel, including the source and drain resistance (RSD) and contact resistance. Where CG is the gate capacitance and l is the carrier mobility in the channel. If one defines DL to be difference between mask channel length and Leff, then
Leff ðV GS Þ ¼ L DLðV GS Þ
ð3Þ
Fig. 3. Transmission line method to extract Leff and RSD.
the n extended source and drain regions under the gate are modulated by VGS and thus DL and RSD are a function of VGS. In order to extract VGS dependent DL, a paired VG method was used as like LDD MOSFETs [10]. The DL at a specific VGS was obtained from the cross point of VGS 0.5 V and VGS +0.5 V lines as shown in inset of Fig. 3. Fig. 4 shows a plot of VGS dependent DL for different LOV. Clearly, DL is largely modulated by VGS due to the presence of the n extended source and drain region. The decrease of DL with increasing VGS is due to the gradual decrease of doping density in the n extended source and drain from high doping region to the intrinsic channel region. Therefore, the Leff is determined by the region where the gate induced electron concentration equals to the doping concentration of the n extended source and drain regions. It is remarkable to note in Fig. 4 that the DL increases with increase of LOV as the previous simulation result [3]. This indicates that the
In order to extract RSD from RTOT, a transmission line method (TLM) was used as shown in Fig. 3. As previous report [3], the common cross point does not exist and the cross points of adjacent voltage lines move toward small values of DL. This indicates that
Fig. 1. Schematic diagram of a fabricated IGZO TFT.
Fig. 4. Plot of VGS dependent DL for different LOV.
D.H. Kim, J.T. Park / Microelectronics Reliability 54 (2014) 2167–2170
doping concentration of n extended region was increased with the increase of LOV due to the area increase of the plasma treatment. Therefore, the increase of ON current with the increase of LOV as shown in Fig. 2 can be attributed to the decrease of Leff. Two interesting aspects can be found from a plot of the change of VTH as a function of channel lengths for different LOV as shown in Fig. 5. The values of VTH were calculated by adjusting VGS with IDS of W/L 0.1 lA. One interesting aspect is that the VTH is decreased with decrease of channel length. Another interesting aspect is the large change of VTH as LOV increases. Since the increase of LOV lead to the decrease of Leff, two aspects are correlated each other. The reason for those interesting aspects can be attributed to the carrier diffusion from n extended region to the intrinsic channel region [11]. Fig. 6. Time dependence of DVTH as a function of LOV after PBS.
3.2. Device degradation with gate overlaps To investigate LOV dependence of VTH instability, we measured VTH shifts (DVTH) with various LOV after positive bias stress (PBS), negative bias stress (NBS) and hot carrier (HC) stress. Fig. 6 shows the time dependence of DVTH as a function of LOV after PBS. The increase of DVTH with stress time is due to the increase of the electron trapped charges. Note that the DVTH decreases with increase of LOV. This interesting result may be attributed to the decrease of Leff with increase of LOV. To confirm the DVTH dependence of channel length, we measured the DVTH with various channel lengths under PBS as shown in Fig. 7. Clearly one can see the decrease of DVTH with the decrease of channel lengths. The explanation for this observation was previously reported that the carrier diffusion from n extended region to the intrinsic channel region shifts the Fermi energy level toward the conduction band edge and thus the trap unoccupied trap states decrease [4]. Fig. 8 shows the time dependence of DVTH as a function of LOV after NBS. The increase of DVTH with NBS stress time was known due to the increase of the hole trapped charges. One can clearly observe that DVTH decreases with increase of LOV. The concrete mechanism for this observation is not known but we believe that the hole injection into the gate dielectric layer may be reduced due to the increase of the electron concentration in the intrinsic channel region which was resulted from the carrier diffusion from n extended region to the intrinsic channel region. Further analysis of the decrease of DVTH with the increase of LOV after NBS is in progress. Fig. 9 shows the time dependence of DVTH as a function of LOV after HC stress. The increase of DVTH with HC stress time is due to the increase of the electron trapped charges. Note that DVTH increases with increase of LOV. Contrary to the device degradation after PBS and NBS, hot carrier induced device degradation was increased with increase of LOV. Since the Leff is reduced with increase of LOV, it is reasonable to speculate that the lateral electric field which brings about hot carrier effects is increased with increase of LOV.
Fig. 5. Plot of the change of VTH as a function of L for different LOV.
Fig. 7. Time dependence of DVTH as a function of L after PBS.
Fig. 8. Time dependence of DVTH as a function of LOV after NBS.
Fig. 9. Time dependence of DVTH as a function of LOV after HC stress.
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4. Conclusion From the electric measurement of inverted staggered IGZO TFTs which the source and drain regions were was exposed to H+ and Ar ion plasma, it was found that the effective channel length was reduced with increase of the gate overlaps. After positive and negative biases stress, the decrease of the threshold voltage shifts with increase of the gate overlaps may be attributed to the carrier diffusion from the n extended source and drain regions to the intrinsic channel region. Since the effective channel length was reduced with increase of the gate overlaps, the hot carrier induced threshold voltage shifts were increased. Acknowledgement This work was supported by the Incheon National University Research Grant in 2013. References [1] Park J, Jeong J, Mo Y, Kim H. Improvements in the device characteristics of amorphous indium gallium zinc oxide thin-film transistors by Ar plasma treatment. Appl Phys Lett 2007;90:262106.
[2] Ahn B, Shin H, Kim H, Park J, Jeong J. Comparison of the effects of Ar and H2 plasmas on the performance of homojunctioned amorphous indium gallium zinc oxide thin film transistors. Appl Phys Lett 2008;93:203506. [3] Jeong J, Hong Y, Jeong J, Park J, MO Y. MOSFET-like behavior of a-InGaZnO thinfilm transistors with plasma-exposed source-drain bulk region. J Display Technol 2009;5(12):495. [4] Ha S, Kang D, Kang I, Han J, Mativenga M, Jang J. Channel length dependent bias-stability of self-aligned coplanar a-IGZO TFTs. J Display Technol 2013;9(12):985. [5] Park J, Kim C, Song I, Kim S, Kang D, Lim H, et al. Source/drain series-resistance effects in amorphous gallium–indium zinc-oxide thin film transistors. IEEE Electron Dev Lett 2008;29(8):879. [6] Suresh A, Muth J. Bias stress stability of indium gallium zinc oxide channel based transparent thin film transistors. Appl Phys Lett 2008;92:033502. [7] Chen T, Chang T, Hsieh T, Lu W, Jian F, Tsai C, et al. Investigating the degradation behavior caused by charge trapping effect under DC and AC gate bias stress for InGaZnO thin film transistor. Appl Phys Lett 2011;99:022104. [8] Lee S, Jeong S, Cho W, Park J. Hot carrier degradation of IGZO thin film transistor under light illumination at elevated temperature. Solid-State Electron 2012;72:88. [9] Cho J, Jung S, Jang K, Park H, Heo J, Lee W, et al. The effect of gate overlap lightly doped drains on low temperature poly-Si thin film transistors. Microelectron Reliab 2012;52:137. [10] Hu G, Chang C, Cha Y. Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET’s. IEEE Trans Electron Dev 1997;34(12):2469. [11] Kang D, Han J, Mativenga M, Ha S, Jang J. Threshold voltage dependence on channel length in amorphous-indium–gallium-zinc-oxide thin film transistors. Appl Phys Lett 2013;102:083508.
Contents lists available at ScienceDirect
Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel
The effect of gate overlap on the device degradation in IGZO thin film transistors Dae Hyun Kim, Jong Tae Park ⇑ Department of Electronics Engineering, Incheon National University, #119 Academi-Ro Yoonsu-Gu, Incheon 406-772, Republic of Korea
a r t i c l e
i n f o
Article history: Received 24 June 2014 Accepted 8 July 2014 Available online 5 August 2014 Keywords: InGaZnO thin film transistor Device reliability Gate overlap
a b s t r a c t The effect of gate overlap on the device degradation in IGZO TFTs treated by H2 and Ar plasma was experimentally investigated after positive and negative gate biases stress and hot carrier stress. Using transmission line method, the effective channel length was extracted with the length of the gate overlaps. After positive and negative biases stress, the decrease of threshold voltage shifts with the increase of the gate overlaps may be attributed to the carrier diffusion from the n extended source and drain regions to the intrinsic channel region. The hot carrier induced threshold voltage shifts were increased with the increase of the gate overlap due to the reduction of effective channel length. Ó 2014 Elsevier Ltd. All rights reserved.
1. Introduction Amorphous IGZO thin film transistors are attractive candidates for pixel drivers in display applications, such as active-matrix organic light emitting diode, active matrix liquid crystal displays, and flexible display due to their transparency and excellent electrical properties, including high mobility and on/off current ratio. A staggered bottom gate structure of IGZO TFT with an etch stopper layer is widely used for transparent display applications, but it has a high parasitic capacitance and series resistance due to the existence of overlap region between gate and source/drain electrode. In order to overcome these disadvantages, a device structure of source/drain formed by plasma etching process with etch stop layer has been introduced instead of the typical lift-off process [1]. It is known that H2 and Ar plasma treatment can improve the film conductivity by increasing electron concentrations of IGZO film without degradation of mobility [2]. In this process, H+ ion can diffuse into IGZO film and acts as a donor and thus the source/drain regions can be highly doped as n+. It was previously reported that the highly conductive region doped by H+ ions can be extended into the channel region and the effective channel lengths of IGZO TFTs could be defined as like those of lightly doped drain (LDD) MOSFETs [3]. The diffusion of H+ ion from the n+ doped source and drain region to the intrinsic channel region leads to that the short channel devices exhibit a more negative initial threshold voltage compared to the long channel devices [4].
⇑ Corresponding author. Tel.: +82 (32) 835 8445; fax: +82 (32) 835 0774. E-mail address: [email protected] (J.T. Park). http://dx.doi.org/10.1016/j.microrel.2014.07.011 0026-2714/Ó 2014 Elsevier Ltd. All rights reserved.
In conventional staggered bottom gate structure of TFTs, the highly n+ doped source/drain region and the gate overlap (LOV) lead to the current distributed over a wider contact area and thus reduce the parasitic resistance [5]. With assumption of gradually doped source/drain region, the simulation result showed that the effective channel length was decreased with increase of LOV and VGS [3]. Therefore, LOV influences the device performance and instability. The device instability of IGZO TFTs was intensively studied under both positive and negative gate bias stress [6,7]. And the drain bias induced hot carrier effect on the device degradation was also reported recently [8]. Although the effect of gate overlap lightly doped drain on low temperature poly-Si thin film transistor was addressed [9], there is no profound study on the effect of LOV on the device degradation in IGZO TFTs within our knowledge. In this work, the effect of LOV on the device degradation in IGZO TFT which was treated by H2 and Ar plasma was experimentally investigated after positive and negative gate biases stress and hot carrier stress. The device instabilities of IGZO TFTs were analyzed with the various length of LOV. 2. Device fabrication and measurement Staggered amorphous IGZO thin film transistors with bottom gate were fabricated on a glass substrate, where Mo was deposited as a gate electrode using RF sputtering. A 200 nm thick SiNx layer was deposited as a gate dielectric material by PECVD at 300 °C. An 50 nm thick amorphous IGZO (1:1:1 mol of Ga2O3:In2O3:ZnO) film was deposited by RF sputtering at a deposition power of 100 W, a working pressure of 6 mTorr in an ambient of Ar with a flow rate of 30 sccm. After defining the active IGZO channel region using
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photolithography and wet etching, SiOx was deposited for the etch stop layer and patterned. Then the etch stop layer was etched by a reactive ion etching method with a gas mixture of Ar and CHF3. During this plasma treatment, the source and drain regions of IGZO layer were exposed to Ar and CHF3 and thus supposed to be highly n+ doped region [2]. The LOV ranging from 0 lm to 3 lm is determined by the extension of exposed source and drain regions. A 150 nm thick Mo layer was deposited and patterned for the source and drain electrodes and then etched by a reactive ion etching. Finally, all devices were annealed in oven at 350 °C for 1 h. Fig. 1 shows the schematic diagram of a fabricated IGZO TFT. The electrical characteristics of the transistors were measured with an Agilent B1500A precision semiconductor parameter analyzer in dark conditions and in air. The gate and/or drain biases were interrupted at fixed times to record the transfer characteristics of the transistor at room temperature. Measurements were made on transistors with a physical gate length (L) ranging from 8 lm to 30 lm and a width (W) ranging from 14 lm to 64 lm.
Fig. 2. Transfer characteristics of IGZO TFTs with L = 25 lm and W = 24 lm for different LOV.
3. Results and discussion 3.1. Electrical characteristics with gate overlaps Fig. 2 shows transfer characteristics of IGZO TFTs with L = 25 lm and W = 24 lm for different LOV. It is remarkable that the transfer curves are shifted negatively and the ON currents are increased slightly as LOV increases. The reason for this interesting observation is believed due to the decrease of the effective channel length (Leff) which is resulted from a highly conductive source and drain regions extended into the intrinsic channel region as previous report [3]. The variation of Leff with the gate overlap will be further discussed. Since the current flows through all contact area under the highly doped source and drain electrode in IGZO TFTs, the total source-to-drain resistance of IGZO TFTs operated in the linear region can be generalized as a function of VGS [10].
RTOT ðV GS Þ ¼ RCH ðV GS Þ þ RSD ðV GS Þ
ð1Þ
where RCH is the effective channel resistance that can be expressed by
RCH ðV GS Þ ¼ Leff ðV GS Þ=W lC G ðV GS V TH 0:5V DS Þ
ð2Þ
RSD is all the resistance outside the channel, including the source and drain resistance (RSD) and contact resistance. Where CG is the gate capacitance and l is the carrier mobility in the channel. If one defines DL to be difference between mask channel length and Leff, then
Leff ðV GS Þ ¼ L DLðV GS Þ
ð3Þ
Fig. 3. Transmission line method to extract Leff and RSD.
the n extended source and drain regions under the gate are modulated by VGS and thus DL and RSD are a function of VGS. In order to extract VGS dependent DL, a paired VG method was used as like LDD MOSFETs [10]. The DL at a specific VGS was obtained from the cross point of VGS 0.5 V and VGS +0.5 V lines as shown in inset of Fig. 3. Fig. 4 shows a plot of VGS dependent DL for different LOV. Clearly, DL is largely modulated by VGS due to the presence of the n extended source and drain region. The decrease of DL with increasing VGS is due to the gradual decrease of doping density in the n extended source and drain from high doping region to the intrinsic channel region. Therefore, the Leff is determined by the region where the gate induced electron concentration equals to the doping concentration of the n extended source and drain regions. It is remarkable to note in Fig. 4 that the DL increases with increase of LOV as the previous simulation result [3]. This indicates that the
In order to extract RSD from RTOT, a transmission line method (TLM) was used as shown in Fig. 3. As previous report [3], the common cross point does not exist and the cross points of adjacent voltage lines move toward small values of DL. This indicates that
Fig. 1. Schematic diagram of a fabricated IGZO TFT.
Fig. 4. Plot of VGS dependent DL for different LOV.
D.H. Kim, J.T. Park / Microelectronics Reliability 54 (2014) 2167–2170
doping concentration of n extended region was increased with the increase of LOV due to the area increase of the plasma treatment. Therefore, the increase of ON current with the increase of LOV as shown in Fig. 2 can be attributed to the decrease of Leff. Two interesting aspects can be found from a plot of the change of VTH as a function of channel lengths for different LOV as shown in Fig. 5. The values of VTH were calculated by adjusting VGS with IDS of W/L 0.1 lA. One interesting aspect is that the VTH is decreased with decrease of channel length. Another interesting aspect is the large change of VTH as LOV increases. Since the increase of LOV lead to the decrease of Leff, two aspects are correlated each other. The reason for those interesting aspects can be attributed to the carrier diffusion from n extended region to the intrinsic channel region [11]. Fig. 6. Time dependence of DVTH as a function of LOV after PBS.
3.2. Device degradation with gate overlaps To investigate LOV dependence of VTH instability, we measured VTH shifts (DVTH) with various LOV after positive bias stress (PBS), negative bias stress (NBS) and hot carrier (HC) stress. Fig. 6 shows the time dependence of DVTH as a function of LOV after PBS. The increase of DVTH with stress time is due to the increase of the electron trapped charges. Note that the DVTH decreases with increase of LOV. This interesting result may be attributed to the decrease of Leff with increase of LOV. To confirm the DVTH dependence of channel length, we measured the DVTH with various channel lengths under PBS as shown in Fig. 7. Clearly one can see the decrease of DVTH with the decrease of channel lengths. The explanation for this observation was previously reported that the carrier diffusion from n extended region to the intrinsic channel region shifts the Fermi energy level toward the conduction band edge and thus the trap unoccupied trap states decrease [4]. Fig. 8 shows the time dependence of DVTH as a function of LOV after NBS. The increase of DVTH with NBS stress time was known due to the increase of the hole trapped charges. One can clearly observe that DVTH decreases with increase of LOV. The concrete mechanism for this observation is not known but we believe that the hole injection into the gate dielectric layer may be reduced due to the increase of the electron concentration in the intrinsic channel region which was resulted from the carrier diffusion from n extended region to the intrinsic channel region. Further analysis of the decrease of DVTH with the increase of LOV after NBS is in progress. Fig. 9 shows the time dependence of DVTH as a function of LOV after HC stress. The increase of DVTH with HC stress time is due to the increase of the electron trapped charges. Note that DVTH increases with increase of LOV. Contrary to the device degradation after PBS and NBS, hot carrier induced device degradation was increased with increase of LOV. Since the Leff is reduced with increase of LOV, it is reasonable to speculate that the lateral electric field which brings about hot carrier effects is increased with increase of LOV.
Fig. 5. Plot of the change of VTH as a function of L for different LOV.
Fig. 7. Time dependence of DVTH as a function of L after PBS.
Fig. 8. Time dependence of DVTH as a function of LOV after NBS.
Fig. 9. Time dependence of DVTH as a function of LOV after HC stress.
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4. Conclusion From the electric measurement of inverted staggered IGZO TFTs which the source and drain regions were was exposed to H+ and Ar ion plasma, it was found that the effective channel length was reduced with increase of the gate overlaps. After positive and negative biases stress, the decrease of the threshold voltage shifts with increase of the gate overlaps may be attributed to the carrier diffusion from the n extended source and drain regions to the intrinsic channel region. Since the effective channel length was reduced with increase of the gate overlaps, the hot carrier induced threshold voltage shifts were increased. Acknowledgement This work was supported by the Incheon National University Research Grant in 2013. References [1] Park J, Jeong J, Mo Y, Kim H. Improvements in the device characteristics of amorphous indium gallium zinc oxide thin-film transistors by Ar plasma treatment. Appl Phys Lett 2007;90:262106.
[2] Ahn B, Shin H, Kim H, Park J, Jeong J. Comparison of the effects of Ar and H2 plasmas on the performance of homojunctioned amorphous indium gallium zinc oxide thin film transistors. Appl Phys Lett 2008;93:203506. [3] Jeong J, Hong Y, Jeong J, Park J, MO Y. MOSFET-like behavior of a-InGaZnO thinfilm transistors with plasma-exposed source-drain bulk region. J Display Technol 2009;5(12):495. [4] Ha S, Kang D, Kang I, Han J, Mativenga M, Jang J. Channel length dependent bias-stability of self-aligned coplanar a-IGZO TFTs. J Display Technol 2013;9(12):985. [5] Park J, Kim C, Song I, Kim S, Kang D, Lim H, et al. Source/drain series-resistance effects in amorphous gallium–indium zinc-oxide thin film transistors. IEEE Electron Dev Lett 2008;29(8):879. [6] Suresh A, Muth J. Bias stress stability of indium gallium zinc oxide channel based transparent thin film transistors. Appl Phys Lett 2008;92:033502. [7] Chen T, Chang T, Hsieh T, Lu W, Jian F, Tsai C, et al. Investigating the degradation behavior caused by charge trapping effect under DC and AC gate bias stress for InGaZnO thin film transistor. Appl Phys Lett 2011;99:022104. [8] Lee S, Jeong S, Cho W, Park J. Hot carrier degradation of IGZO thin film transistor under light illumination at elevated temperature. Solid-State Electron 2012;72:88. [9] Cho J, Jung S, Jang K, Park H, Heo J, Lee W, et al. The effect of gate overlap lightly doped drains on low temperature poly-Si thin film transistors. Microelectron Reliab 2012;52:137. [10] Hu G, Chang C, Cha Y. Gate-voltage-dependent effective channel length and series resistance of LDD MOSFET’s. IEEE Trans Electron Dev 1997;34(12):2469. [11] Kang D, Han J, Mativenga M, Ha S, Jang J. Threshold voltage dependence on channel length in amorphous-indium–gallium-zinc-oxide thin film transistors. Appl Phys Lett 2013;102:083508.