s 7-bit time-interleaved Quasi C-2C SAR ADC using voltage-comparator time-information

Accepted Manuscript Regular paper A 1.8V 3GS/s 7-bit Time-Interleaved Quasi C-2C SAR ADC using VoltageComparator Time-Information Hamed Nasiri, Abdolreza Nabavi PII: DOI: Reference:

S1434-8411(17)30514-9 http://dx.doi.org/10.1016/j.aeue.2017.08.028 AEUE 52024

To appear in:

International Journal of Electronics and Communications

Received Date: Revised Date: Accepted Date:

8 March 2017 6 July 2017 20 August 2017

Please cite this article as: H. Nasiri, A. Nabavi, A 1.8V 3GS/s 7-bit Time-Interleaved Quasi C-2C SAR ADC using Voltage-Comparator Time-Information, International Journal of Electronics and Communications (2017), doi: http://dx.doi.org/10.1016/j.aeue.2017.08.028

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A 1.8V 3GS/s 7-bit Time-Interleaved Quasi C-2C SAR ADC using VoltageComparator Time-Information Hamed Nasiri, Faculty of Electrical and Computer Eng., Tarbiat Modares University, Tehran, Iran Abdolreza Nabavi, Faculty of Electrical and Computer Eng., Tarbiat Modares University, Tehran, Iran

A 1.8V 3GS/s 7-bit Time-Interleaved Quasi C-2C SAR ADC using VoltageComparator Time-Information Abstract—This paper presents a 7-bit 15× interleaved SAR ADC that operates up to 3GS/s, using 180nm CMOS technology. The ADC utilizes the transient information of a dynamic SAR voltage-comparator to resolve 2 bits per clock cycle, using a time-comparator block. Thus, only 5 clock cycles are needed to resolve 7 bits. This results in speed improvement of about 60%, compared to conventional ADC. Also, an improved Quasi C-2C DAC structure with reduced internal node swing and reduced switching activity are utilized, which decreases the power consumption of DAC up to 65%. We employ the above techniques in designing a 7-bit SAR ADC, in which 3 bits are resolved with time-comparator blocks and 4 bits are resolved with a voltage-comparator. To calibrate the proposed time-comparator block, a calibration process is proposed. ADS simulation of the ADC illustrates an ENOB (Effective Number of Bits) > 6.5-bit and SFDR (Spur Free Dynamic Range) = -52.8dBc for a single SAR converter with sampling at 200MS/s. For the time-interleaved SAR ADC with 15 single SAR converters, ENOB is 6.15-bit and SFDR = -45dBc with sampling at 3GS/s up to Nyquist frequency. This ADC consumes 150mW at 1.8V supply and achieves a Figure-of-Merit (FoM) of 700fJ/conv-step. Index Terms— Successive approximation analog-to-digital converter (SAR ADC), Timeinterleaved, Quasi C-2C DAC, Time-comparator, Voltage-comparator. 1. INTRODUCTION Today’s wireless communication systems require analog-to-digital converters with several GHz bandwidths [1]–[3] and moderate resolutions of about 5 to 6 bits [4]. These applications typically have severe power and cost constraints, which is challenging using standard CMOS process.

Among various ADC architectures, SAR ADC is known as an excellent low-energy and highly scalable architecture [5], [6]. Some research works have been recently proposed to reduce the power consumption and increase the speed of SAR ADC. A ternary SAR (TSAR) ADC was proposed in [7], which can provide accuracy, speed, and power benefits. This utilizes transient information of voltage-comparator to reduce the conversion-time. Also, it creates full half-bit redundancy that allows residue shaping, providing an additional 6 dB of signal-to-quantizationnoise ratio (SQNR). However, this structure needs 10 clock cycles to resolve 10 bits, which makes it suitable for low-speed ADCs. A time-interleaved SAR ADC was presented in [1], which utilizes a new C-2C structure with small-area and new background calibration scheme for comparator offset as well as radix calibration. However, it needs two input sampling switches for each C-2C DAC and has a discharge capacitive path (with large capacitor) that increases the intermediate node parasitic capacitance. This path needs some extra switches that make the digital-control part of ADC complex. An energy-efficient SAR ADC is presented in [8], which is suitable for ultra-low power applications. The most important innovation in this structure to minimize DAC hardware and power consumption is a 2 bits/step reference scheme based on a hybrid R-2R/C-3C DAC. But this structure is suitable for low speed ADCs. This paper presents new techniques to reduce the power and increase the speed, most important of which are: 1) resolving 2 bits/step by using the time information of voltage-comparator by means of time-comparator that increases the speed by 1.6 times, since only 5 clock cycles are needed to resolve 7 bits instead of 8 clock cycles used in conventional structure, 2) an improved Quasi C-2C DAC, in which the number of capacitors are reduced and the voltage-swing in intermediate nodes is decreased by half, compared to the C-2C DAC structure used in [1]. Thus,

the power consumption is reduced up to 65%, and 3) a calibration scheme of time-comparator, which can be employed in time interleaved converters. This paper is organized as follows. Section 2 presents the utilization of time information of voltage-comparator to resolve bits. Section 3 describes the proposed Quasi C-2C DAC. Section 4 describes the time-interleaved topology of converter. Section 5 presents the simulations results of the proposed converter in ADS. Section 6 concludes the paper. 2. Utilizing Time Information of Voltage-Comparator In [7], a time-comparator block has been used to decrease the DAC switching energy. This is then employed in a SAR ADC with reduced power dissipation and increased speed. In this section, we describe a technique to employ the time information of a voltage-comparator for resolving 2 bits per clock cycle in a SAR ADC using a time-comparator. 2.1. Analysis of Time Information in Voltage-Comparator Assume that the voltage-comparator is a single-pole system. Thus, its transfer function can be described as: (1)

Where A is the gain of voltage-comparator and

is the time constant of voltage-comparator.

Eq.1 provides the insights into the technique which employs the time information of voltagecomparator. Assume that at time t1, the input voltage value is Vin1 and the value of voltagecomparator output is Vout1. When at t1 the value of Vout is lower than Vout1, it can be inferred that the value of input voltage is lower than Vin1 and vice versa. This time information of voltagecomparator is utilized to indicate the input voltage range. Assume that the input node of a time-comparator is connected to the output of a voltagecomparator. Time-Comparator is designed to compare its input voltage with a specified voltage

value (Vin-T.Comp-desired) at the rising edge of its clock, whose clock has a certain delay compared to that of voltage-comparator. This delay corresponds to the bit that is resolved by timecomparator. The delay can be obtained by: (2)

In (2), K denotes the bit number, e.g. K=7 represents the least significant bit in 7-bit ADC. For resolving the MSB bit, the voltage-comparator decides whether the input voltage is above (below) Vref/2. In order to resolve the next MSB at the same time by using the time information of voltage-comparator, the time-comparator should determine that the absolute value of input voltage is above Vref/4 or not. Therefore, it is determined that the input voltage is in which range of [0, Vref/4], [Vref/4, Vref/2], [Vref/2, 3Vref/4] and [3Vref/4, Vref]. In other words, to resolve the next MSB by time-comparator, first we calculate the corresponding delay time (

) using

(2). At this time, if the voltage-comparator output is equal to or more than Vin-T.Comp-desired, the absolute value of input voltage of voltage-comparator is more than Vref/4 and vice versa. Fig. 1 illustrates that how the input voltage is divided by comparators for the above mentioned procedure.

Volt Comp

Time Comp

Vref /4

Comp Output =1

Comp Output =0

-Vref /4

Fig. 1: Dividing the input voltage by Time-comparator and Voltage-comparator As seen in (2), when K is low, the delay time is small. Therefore, in resolving the MSB, the reliability of time-comparator is less than when resolving the list significant bit (LSB). Thus, in the first-step just the voltage-comparator works, while from the second-step the time-comparator starts its operation. As a result, the voltage-comparator decides the bits with K = 1, 2, 4, and 6. Also, for k= 3, 5, and 7 the time-comparator resolves the bits. By this strategy we need four steps to resolve 7 bits. 2.2. Proposed Time-Comparator Structure As mentioned above, the time-comparator resolves the 3rd, 5th, and 7th MSBs. Thus, the timecomparator should satisfy the characteristics shown in Fig. 2.

-Vref/8

Vref/8

VoutT-Comp

VoutT-Comp

VoutT-Comp

VinComp

a) In third most significant bit

-Vref/32

Vref/32

VinComp

b) In 5th most significant bit

-Vref/128

Vref/128

VinComp

c) In 7th most significant bit

Fig. 2: Curves that should be satisfied by time-comparator In order to satisfy the above characteristics for time-comparator, we take into account the voltage value that the time-comparator compares with the output of Voltage-Comparator (Vin-T.Comp-

desired),

and the time-delay between time-comparator and voltage-comparator clocks. The

structure in Fig. 3 can take into account the above-mentioned voltage value. CAP DAC Time Comp,V1 Time Comp,V2 Time Comp,V3

+

SAR Vdc Clock

DOUT

Time Comp,V1 Time Comp,V2 Time Comp,V3

-

Time delay

`

Fig. 3: The SAR ADC structure by using first parameter This structure needs six time-comparator blocks and hence has some disadvantages. First, the output load of voltage-comparator is very high, which degrades the speed of voltage-comparator. Second, the calibration of time-comparator blocks in this structure is difficult, since the calibration requires changing voltage levels which are related to the design parameters of timecomparator. Fig. 4 illustrates the structure which takes into account the delay between the clocks of timecomparator and voltage-comparator. CAP DAC +

Time Comp

SAR

Vdc Clock

`

DOUT

Time Comp

-

Time Delay1 Time Delay2 Time Delay3

Fig. 4: The proposed SAR ADC structure by using time-delay parameter The proposed structure can solve the above-mentioned disadvantages of structure in Fig. 3. Each output node of voltage-comparator is loaded by just one time-comparator instead of three timecomparator blocks in Fig. 3. Also, the calibration scheme in Fig. 4 is easier than that in Fig. 3,

since the structure in Fig. 4 needs to calibrate the time delays instead of voltage levels in Fig. 3. The calibration can be easily performed by using the capacitor banks in the clock path to create a desired delay. The value of these capacitors can be easily programed after implementation of ADC. Therefore, the proposed structure in Fig. 4 is chosen for implementation. The single-input timecomparator block in this structure compares the input voltage with a specified voltage value at the desired time. Thus, the time-comparator samples the input at the clock rising edge. In other words, this edge-triggered circuit is sensitive to input when the clock signal switches from low to high, i.e. it operates like a TSPC type D-flip-flop. As Fig. 5 shows, this circuit has an input voltage node and an input clock signal. At rising edge of clock signal, this circuit compares the input voltage with a specified voltage value, which is a design parameter of this circuit. This value, referred to as Vin-T.Comp-desired, can be calculated after designing the circuit. Strictly speaking, if the input voltage of this circuit is between zero and Vin -T.Comp-desired, it will recognize the input as logic zero; and if the input voltage is between Vin-T.Comp-desired and VDD, it will recognize the input as logic one. Thus, this time-comparator circuit has two important parameters. First, the start of rising edge, which occurs with a delay corresponding to the required delay for each bit. This delay can be changed by using a variable time delay block. Second, the value of Vin-T.Comp-desired, which is set as a design parameter by proper transistors sizing.

Fig. 5: A TSPC type D flip-flop circuit which is used as time-comparator

2.3. Time-Comparator Calibration As explained above, two important parameters in time-comparator are the clock time-delay and Vin-T.Comp-desired, which switches the output state of time-comparator. These parameters are chosen in the design process of ADC to satisfy the characteristics shown in Fig. 2. Nevertheless, process variation will alter these parameters. Therefore, a calibration scheme is needed to adjust them to their nominal values. To perform the calibration after fabrication, it is enough to adjust the timedelay values shown in Fig. 4, as explained below. Assume that after ADC fabrication, the time-comparator has the actual input voltage value of Vin-T.Comp-desired-fab at which its output is switched. It is expected that time-comparator output is switched when each of the three different input voltage values—Vref/8, Vref/32 and Vref/128 corresponding to the 3rd, 5th, and 7th bits, respectively, will be resolved with time-comparator by applying the respective delay time values, i.e. Time-Delay1, Time-Delay2, and Time-Delay3. At these times the input (output) voltage value of time-comparator (voltage-comparator) should be equal to Vin-T.Comp-desired-fab. To satisfy this, the time-delay values should be adjusted after fabrication. For example, to adjust Time-Dealy1, which corresponds to 3rd bit (Vref/8), the voltage of Vref/8 should be applied to the input of voltage-comparator and Time-Delay1 should be adjusted to the minimum value. Then, Time-Delay1 is increased step-by-step until the output of timecomparator switches to logic one. Note that if the Time-Delay1 value is smaller (equal to or more) than the expected value, the output of time-comparator will be low (high). In this way, the desired value for Time-Delay1 is obtained.

In the next step with similar technique, the other two time-delay values are adjusted. The calibration scheme is illustrated in Fig. 6. This calibration scheme can be performed frequently when the ADC channel in time-interleaved topology is off. START

Vin_v_Comp = Vref / 128 Tdelay1 = Tmin1

Time_comp_out == 1

NO

Tdelay1 = Tdelay1+ T

NO

Tdelay2 = Tdelay2+ T

NO

Tdelay3 = Tdelay3+ T

YES

Vin_v_Comp = Vref / 32 Tdelay2 = Tmin2

Time_comp_out == 1 YES

Vin_v_Comp = Vref / 8 Tdelay3 = Tmin3

Time_comp_out == 1 YES END

Fig. 6: The calibration scheme of time comparator 2.4. The Schematic of Voltage-Comparator A two-stage dynamic comparator is chosen because of its advantages compared to one-stage dynamic comparators [9]. The schematic of the voltage-comparator used in the proposed C-2C SAR ADC along with the control signals are shown in Fig.7. It consists of a low-gain preamplifier (M1-M4) followed by a latch (M9-M15). As we expect, the voltage-comparator should have exponential output responses with different time constants for different input voltages. As Fig. 8 shows, the voltage comparator provides the proper output voltage for three different input voltages.

VDD M3

M5

M4

M6

Latch_d

M9

M10 bias2

M7 Latch_b

M8

In+

M1

M2

M15

InM13 M11

Latch_b bias

M12 M14

Latch_b

Mbias

Fig.7: The schematic of voltage-comparator along with control signals 1.8 1.6 1.4

Input=LSB Input=4*LSB Input=16*LSB

output (V)

1.2 1 0.8 0.6 0.4 0.2 0 -0.2 0

0.2

0.4 Time (ns)

0.6

0.8

Fig.8: The output of voltage-comparator vs. time for three different input voltages 3. Proposed Quasi C-2C DAC Structure Fig. 9 illustrates the C-2C DAC proposed in [1]. This DAC consists of SA (SR) switches in order to charge (discharge) the output node; and three sets of capacitors, 2CU, CU, and CU/2. Also, it incorporates two reference voltages, Vmin and Vmax. The capacitors with sizes 2C U and CU are implemented as Metal-Finger-Capacitors (MFC). The capacitors with size CU/2 are integral part of DAC, which are equal to the sum of parasitic capacitances and variable capacitor banks at each intermediate node. These variable capacitor banks are used to calibrate the ratio of

capacitors after fabricating the ADC. Therefore, this structure can solve the parasitic capacitance problem in C-2C DACs. In addition, the capacitive load at the input is small; therefore, this structure significantly improves the bandwidth, especially in time-interleaved architectures. In technologies with relatively long channel length, such as 180nm CMOS with high parasitic capacitance of switches and other elements, the design of high speed ADC with this structure is challenging. In the following section, we introduce a new C-2C structure suitable for technologies with relatively long channel length. 3.1. Proposed Quasi C-2C DAC Structure This section describes the proposed techniques to modify the basic C-2C DAC structure in Fig. 9 and to obtain the new structures illustrated in Fig. 10, Fig. 11, and Fig. 12.

Fig. 9: Basic C-2C DAC proposed in [1] The first technique is eliminating the discharge path of the structure in Fig. 9. The discharge path includes 2C capacitors and their respective series switches. As an alternative technique, an additional state has been added to the intermediate node states, as illustrated in Fig. 10.

Vin

Cu/2

Cu

Cu/2 Cu

Cu

Vin

Cu

Sreset

Vmin

Vmed

Vmin Vmed Vmax

Vmin Vmed Vmax

Vmin Vmed Vmax

`

Fig. 10: The first proposed DAC The new three levels should satisfy the conditions in Eq. 3

(3) In this new structure, at the beginning of searching process all intermediate nodes are connected to Vmed. Then, if it needs to charge the DAC output, the corresponding intermediate node will connect to Vmax. Further, if it needs to discharge the output of DAC, the corresponding intermediate node will connect to Vmin. The above techniques provide some advantages. First, die area and parasitic capacitance of the intermediate nodes are reduced by eliminating 2C capacitors from the intermediate nodes. Second, the settling time of DAC is decreased by eliminating the switches that have been connected to 2C capacitors. Third, the switching energy of DAC is decreased. However, the proposed structure requires three reference voltages instead of two reference voltages needed in the basic structure. Suppose that Vref = 0.8V, so Vmax will be near 1.8V. By taking into account that the value of Vdd in 180nm CMOS technology is 1.8V, the intermediate node voltages can be more than Vdd. Thus, the switches in intermediate nodes should be designed with high Vt transistor, i.e. transistor with length more than minimum feature size. This is not recommended in high speed design.

Furthermore, the Sreset switch at the output node of DAC in both structures should be designed with high speed and very low parasitic capacitance. Design of this switch in 180nm CMOS technology with desired characteristics is challenging. The proposed structure in Fig. 11 solves the above problems.

S1

Vmax Vmed Vmin

2Cu

Vmax Vmed Vmin

Vmax Vmed Vmin

Vin

Vdc

S2

Sreset Vout Cu

Cu

Cu/2

Cu

Fig.11: The second proposed DAC The new three levels of the second proposed structure satisfy the conditions in Eq. 4

(4) In this case, if Vref = 0.8V, the reference voltages can be selected as (0.2V, 0.6V and 1V). In this case, the voltage in intermediate nodes are always less than Vdd. Also, the switching energy of DAC is decreased, since the voltage swing at the intermediate nodes (and respective capacitors) is declined by half. As illustrated in Fig. 11, this structure needs a capacitor equal to CU to connect the output node to ground. The parasitic capacitance at the output is merged with the calibration capacitor in this node to create a capacitor equal to CU from output node to ground. This means that their values are adjusted to CU by calibration. The parasitic capacitor of Sreset switch can be merged into CU capacitor. Therefore, the design of Sreset switch in this structure will be easier than previous one. Also, in this structure, one of the sampling switches is eliminated.

The final proposed DAC structure that is used in SAR ADC will resolve two bits per clock cycle. In the structure of Fig. 11, when a bit is applied to DAC, the respective intermediate node will be connected to a DC voltage. Thus, other bits at the right side of that intermediate node cannot be applied until the previous node is floated. It means that two bits cannot be applied at the same time in this structure. In order to change the structure to resolve two bits in one cycle, the paths of two bits should be separated from corresponding intermediate nodes to the output node, as proposed in Fig. 12.

Cu

2Cu

Vmax Vmed Vmin

Cu

B Vmax Vmed Vmin

S1

A Cu/2

2Cu

Sreset Vout

Vmax Vmed Vmin

Vmax Vmed Vmin

Vin

Vdc

S2

I

C

Vmax Vmed Vmin

2Cu

Vmax Vmed Vmin

Cu

Cu/2

Cu/2

Cu

D

E

F Cu

Cu/2

Cu/2

Cu

Cu

Fig.12: The final proposed Quasi C-2C DAC The DAC in Fig. 12 is utilized in the proposed SAR ADC, which operates as follows. 1) Initially, the input voltage is applied through input sampling switch, and Sreset switch resets the output node. Here, S1 is closed, S2 is open, and all intermediate nodes on the right side of the output node are connected to Vmed. 2) At the second clock cycle, Sreset and S1 switch off while S2 switches on. Then, the node I will be connected to Vdc (DC value of input voltage). After the settling time of output node, S2 will

switch off. Now, the voltage comparator compares the input voltage with ground and resolves the MSB. If the output node is needed to be charged, the node A will switch from Vmed to Vmax. Further, if the output node is needed to be discharged, the node A will switch from Vmed to Vmin. 3) At the third clock cycle, first the voltage-comparator resolves the second MSB. After the respective delay (Time-delay1), the time-comparator resolves the third MSB. Then, node A will be floated and the next states (either Vmin or Vmax) of nodes B&C will be determined based on the resolved two bits in this cycle. 4) At the 4th clock cycle, first the voltage-comparator resolves the 4th MSB. After the corresponding delay (Time-delay2), the time-comparator resolves the 5th MSB. Now nodes B&C will be floated and the next states of nodes D&E will be determined, considering the two resolved bits in this cycle. 5) At the 5th clock cycle, the voltage-comparator resolves the 6th bit. After the respective delay (Time-delay3), the time-comparator resolves the 7th bit (LSB). Finally, DAC will switch to its initial state. Although node F is not used in this process, it will be used in time-comparator calibration process. In the above proposed method, 7 bits are resolved in 5 clock cycles. 3.2. Switching Energy of Proposed DAC In this section, the switching energy of proposed DAC is calculated and compared to that in the basic DAC [1]. As expected, the switching energy of the proposed DAC is lower than the basic one proposed in [1], because of: 1) The voltage change at intermediate nodes is declined by half. 2) The equivalent capacitance value of all intermediate nodes is decreased. Since, the discharge paths in the proposed DAC are eliminated, the charge transfer between capacitors is decreased.

3) The proposed DAC needs less state change compared to basic DAC structure. For example, in a 5-bit ADC with proposed architecture, the DAC state changes two times, while in the basic ADC [1] it changes four times. In order to compare the switching energy, we make the assumptions explained below for both DACs. 1) For the basic DAC [1], assume that Vmin=0.2V, Vmax=1V, and Vref=0.8V. 2) For the proposed DAC structure assume that Vmin=0.2V, Vmed=0.6V, Vmax=1V, and Vref=0.8V. Thus, the switching energy for both DACs are calculated as illustrated in Fig. 13. 31Vref / 32? 15Vref / 16? 29Vref / 32? 7Vref / 8? 27Vref / 32? 13Vref / 16? 25Vref / 32? 3Vref / 4? 23Vref / 32? 11Vref / 16? 21Vref / 32? 5Vref / 8? 19Vref / 32? 9Vref / 16? 17Vref / 32? Vref / 2? 15Vref / 32? 7Vref / 16?

13Vref / 32? 3Vref / 8? 11Vref / 32? 5Vref / 16? 9Vref / 32? Vref / 4? 7Vref / 32? 3Vref / 16? 5Vref / 32? Vref / 8? 3Vref / 32? Vref / 16? Vref / 32?

Fig.13: a) The diagram of switching energy for C-2C DAC [1] 15 Vref / 16? 13 Vref / 16? 3 Vref / 4? 11 Vref / 16?

9 Vref / 16? Vref / 2? 7 Vref / 16?

Vref / 4?

5 Vref / 16? 3 Vref / 16? Vref / 16?

Fig.13: b) The diagram of switching energy for proposed Quasi C-2C DAC

The switching energy diagram in Fig. 13 is shown for 5 bits. It should be noted that a negative switching energy implies that the DAC gives energy back to the reference voltage sources. 3.3. Proposed Quasi C-2C DAC Power Saving Calculation As shown in Fig. 13, the switching energy in the proposed DAC is expected to reduce. To show this, the switching energy of these two DACs are calculated with MATLAB. Fig. 14 shows the results of these calculations which illustrate a reduction of about 65% in switching energy of the proposed DAC compared to that in the basic one [1].

14 [1] C-2C

Energy Per Code Conversion(CVref 2)

12

Proposed C-2C Average of [1] C-2C

10

Average of Proposed C-2C

8

6

4

2

0

20

40

60

80

100

120

Code

Fig.14: Switching energy versus output Codes 4. Time-Interleaved Topology of Converter This section describes the structure of a time-interleaved ADC using 15 single Quasi C-2C SAR ADCs proposed in the previous section. Each SAR ADC resolves 7 bits and needs 5 clock cycles to convert an input sample. Thus, it samples the input signal at every 5 clock cycles. Therefore, 5 SAR ADCs can be time-interleaved by a single clock signal without using different clock phases. A 3GHz clock is used in this design, which is divided by 3 into 3 different phases by the circuit shown in Fig. 15. Each phase is utilized for 5 time-interleaved ADCs. As the proposed SAR

ADC operates at 200MS/s, 15 time-interleaved converters can operate at 3GS/s. Fig. 16 shows the timing diagram of the proposed 15 x time-interleaved 7-bit SAR ADCs.

Ckout(0) 0

3 GHz

NOR 0

0

D

Q

D

Q

Ckout(120)

Ckin

Ckout(240) CKin Ckout(0) Ckout(120)

Ckout(240)

Fig.15: Three different phase clocks generation

ADC 1

ADC 2 ADC 3 ADC 4 ADC 5 ADC 6

ADC 7 ADC 8 ADC 9 ADC 10 ADC 11 ADC 12

ADC 13 ADC 14 ADC 15

Vin(nT) Vin(nT) Vin(nT) Vin(nT) Vin(nT) Vin(nT+15T) Bit4,3 Sampling MSB Bit6,5 Bit2,1 Sampling Vin(nT+T) Vin(nT+16T) Vin(nT+T) Vin(nT+T) Vin(nT+T) Vin(nT+T) Bit2,1 Sampling Bit6,5 Bit4,3 Sampling MSB Vin(nT+2T) Vin(nT+17T) Vin(nT-13T) Vin(nT+2T) Vin(nT+2T) Vin(nT+2T) Vin(nT+2T) Bit2,1 Sampling Bit2,1 MSB Bit6,5 Bit4,3 Sampling Vin(nT+3T) Vin(nT+3T) Vin(nT-12T) Vin(nT+3T) Vin(nT+3T) Vin(nT+3T) Sampling MSB Bit2,1 Bit2,1 Bit6,5 Bit4,3 Vin(nT+4T) Vin(nT+4T) Vin(nT+4T) Vin(nT+4T) Vin(nT-11T) Vin(nT+4T) Bit2,1 Sampling MSB Bit6,5 Bit2,1 Bit4,3 Vin(nT-10T) Vin(nT+5T) Vin(nT+5T) Vin(nT+5T) Vin(nT+5T) Vin(nT-10T) Vin(nT+5T) Bit2,1 Bit2,1 Sampling MSB Bit6,5 Bit4,3 Bit4,3 Vin(nT-9T) Vin(nT+6T) Vin(nT+6T) Vin(nT-9T) Vin(nT+6T) Vin(nT+6T) Bit4,3 Sampling MSB Bit2,1 Bit4,3 Bit6,5 Vin(nT-8T) Vin(nT+7T) Vin(nT+7T) Vin(nT+7T) Vin(nT-8T) Vin(nT+7T) Bit4,3 Sampling MSB Bit6,5 Bit2,1 Bit4,3 Vin(nT-7T) Vin(nT+8T) Vin(nT+8T) Vin(nT+8T) Vin(nT-7T) Vin(nT-7T) Vin(nT+8T) Bit2,1 Sampling MSB Bit6,5 Bit4,3 Bit6,5 Bit4,3 Vin(nT-6T) Vin(nT+9T) Vin(nT+9T) Vin(nT+9T) Vin(nT-6T) Vin(nT-6T) Bit4,3 Sampling MSB Bit6,5 Bit2,1 Bit6,5 Vin(nT-5T) Vin(nT+10T) Vin(nT+10T) Vin(nT+10T) Vin(nT-5T) Vin(nT-5T) Bit4,3 Sampling MSB Bit6,5 Bit6,5 Bit2,1 Vin(nT-4T) Vin(nT-4T) Vin(nT-4T) Vin(nT+11T) Vin(nT+11T) Vin(nT+11T) Vin(nT-4T) MSB Bit6,5 Bit4,3 Sampling MSB Bit6,5 Bit2,1 Vin(nT-3T) Vin(nT-3T) Vin(nT-3T) Vin(nT+12T) Vin(nT+12T) Vin(nT-3T) Bit2,1 MSB Bit6,5 Sampling MSB Bit4,3 Vin(nT-2T) Vin(nT-2T) Vin(nT+13T) Vin(nT+13T) Vin(nT-2T) Vin(nT-2T) Bit6,5 Bit4,3 Sampling MSB MSB Bit2,1 Vin(nT-T) Vin(nT+14T) Vin(nT+14T) Vin(nT-T) Vin(nT-T) Vin(nT-T) Bit2,1 Sampling MSB Bit4,3 MSB Bit6,5

Fig.16: Timing diagram of the proposed 15x time-interleaved 7-bit SAR ADCs Consequently, the time-interleaving scheme is implemented with 15 ADCs as shown in Fig. 17, with 3 extra ADCs (ADCa, ADCb, and ADCc) to allow background calibration [1] of the mismatch related problems, as modeled in [10].

Out Clk (0)

Clock

Clock Divide by 3 with 3 different phases

Out Clk (+120) Out Clk (+240)

Delay Line Delay Line Delay Line Delay Line Delay Line Delay Line

ADC 1

Delay Line Delay Line Delay Line Delay Line Delay Line Delay Line

ADC 6

Delay Line Delay Line Delay Line Delay Line Delay Line Delay Line

ADC 2 ADC 3 ADC 4 ADC 5 ADC a

ADC 7 ADC 8 ADC 9 ADC 10 ADC b

ADC 11 ADC 12 ADC 13

ADC 14 ADC 15 ADC c

Fig.17: Simplified schematic of the overall time-interleaved ADC Each ADC, which runs at 1GHz, has a programmable delay line. The programmable delay line is utilized to align the clock edges of the SAR ADCs to eliminate the clock skew problem resulted from interleaving. ADC outputs are fed into output drivers which consist of register blocks and strong output buffers that are capable of driving the long output buses. 5. Simulation Results The proposed ADC is designed in 180nm CMOS technology and simple transient simulation is performed in ADS software. Each SAR ADC is designed for input voltage range of 0 - 1.6V. The input range of the proposed SAR ADC can be changed by changing the DC voltage value. For example, the input voltage range can be -0.8V - +0.8V. For the proposed DAC as shown in Fig. 12, Vdc=0.8, Vmin=0.2V, Vmed=0.6V, Vmax=1V and Cu=300fF

(the unit capacitor) [11] are chosen.

Simulation of the proposed ADC shows that a single SAR ADC consumes 10mW from a 1.8V supply. Fig. 18 shows the percentage power distribution of a proposed SAR ADC.

Fig.18: Power distribution of the unit SAR ADC As shown in Fig. 18, the most percentage of power is dissipated by digital parts. This is because: 1) The digital parts are designed for high speed rather than low power consumption. 2) The proposed ADC is designed in a technology with high Vdd and for high speed. Design of this structure using finer CMOS technologies can result in very lower power consumption. As shown in Fig. 18 two time-comparators are used, which have lower power dissipation than voltage comparator. Conventional SAR ADC that extract two bits in each clock cycle has three DACs and three voltage comparators with their corresponding digital parts [12]. So, the proposed SAR ADC that can extract two bits in each clock cycle has very lower power dissipation than conventional one. The static linearity performance was tested using the code density method. A sampling rate of 200 MS/s and an input ramp signal from 0 to 1.6V were used. A total of 1280 samples, 10 samples for each digital code, were collected for each run. Fig. 19 shows the differential nonlinearity (DNL) and integral nonlinearity (INL) of the ADC output. The maximum calculated DNL and INL are 0.75LSB and 0.9LSB, respectively.

a) DNL plot

b) INL plot

Fig.19: Simulated DNL and INL plots of the proposed ADC . The dynamic performance is calculated using single tone testing. Fig. 20 shows the Fast Fourier Transform (FFT) spectra of a single SAR ADC output with 90 MHz full-scale sinusoidal input with 9600 samples, which is sampled at 200 MS/s. The SINAD and SFDR calculated are 40.89dB and -52.8dBc, respectively. The single SAR ADC achieved an ENOB (effective number of bits) of 6.5 bits. In Fig. 21 the calculated ENOB for three different corner simulations is plotted over a series of input signals with different frequencies, sampled at 200 MS/s.

Fig. 20: simulated output spectrum showing the SINAD and SFDR values of a single Quasi C2C SAR ADC when the input frequency is 90MHz.

7.2 FF, Temp=-40 C, VDD=2 V TT, Temp=25 C, VDD=1.8 V SS, Temp=125 C, VDD=1.6 V

7 6.8

ENOB (bit)

6.6 6.4 6.2 6 5.8 5.6 5.4 0

10

20

30

40 50 60 Input frequency (MHz)

70

80

90

100

Fig. 21: Simulated ENOB with input frequency of a single Quasi C-2C SAR ADC in the Nyquist zone Fig. 22 shows the Fast Fourier Transform (FFT) spectra of the time-interleaved SAR ADC output. The input sinusoidal signal with frequency of 1.25GHz are sampled at 3GS/s, 9600 samples are used. The calculated SINAD and SFDR are 38.8dB and -45dBc, respectively. The time-interleaved SAR ADC achieved an ENOB of 6.15 bits. In Fig. 23 the calculated ENOB for three different corner simulations is plotted over a series of input signals with different frequencies, sampled at 3GS/s. The time-interleaved ADC achieves FoM of 700 fJ/conversionstep.

Fig. 22: simulated output spectrum showing the SINAD and SFDR values of the time-interleaved SAR ADC when the input frequency is 1.25GHz.

6.5 FF, Temp=-40 C, VDD=2 V TT, Temp=25 C, VDD=1.8 V SS, Temp=125 C, VDD=1.6 V

ENOB (bit)

6.3

6.1

5.9

5.7

5.5 0

0.1

0.2

0.3

0.4

0.5

0.6 0.7 0.8 0.9 Input frequency (GHz)

1

1.1

1.2

1.3

1.4

1.5

Fig. 23: Simulated ENOB with input frequency of the time-interleaved SAR ADC in the Nyquist zone Table 1 compares the proposed time-interleaved ADC with ADCs in [1, 13, 14, 15]. The results of ADCs in [1, 14, 15] are measured results but the results of the proposed ADC and the ADC in [13] are simulation results using the same technology. Table 1: Performance comparison Source

[1]

[15]

[14]

[13]

This work

Type of Results

Measured

Measured

Measured

Simulation

Simulation

Technology

45nm LP

65nm LP

90nm LP

0.18um

0.18um

Channel#

16

2

16

3

15

Supply Voltage(V)

1.1

1.2

1.3

1.8

1.8

Input Range(Vp-p(V))

1

-

1

1

1.6

Sampling Rate(S/sec)

2.5GS/s

1GS/s

1.6GS/s

700MS/s

3GS/s

Resolution(bit)

7

6

6

4

7

ENOB(bit)

5.4

5

4.75

3.68

6.15

Power Consumption(mW)

50

6.27

20.1

23.3

150

FOM(fJ/conversion-step)

480

210

460

2500

700

6. Conclusion This paper presented a 7-bit 3GS/sec Nyquist SAR ADC in 180nm CMOS technology, utilizing 15 time-interleaved SAR ADC blocks. Each SAR ADC employs the time information of voltage-comparators, which increases the speed by 1.6 times. An improved Quasi C-2C DAC structure was proposed, which reduces the power consumption up to 65%. Also, a new calibration scheme for time-comparator was presented. This ADC can be used in wideband receivers, such as OFDM systems for high-speed short-range wireless communications. ADS simple transient simulation results show that the proposed ADC has an ENOB (Effective Number of Bits) = 6.5 bits and SFDR (Spur Free Dynamic Range) = -52.8dBc for a single SAR ADC. For the time-interleaved SAR ADC, ENOB = 6.15 bits, and SFDR = -45dBc up to the Nyquist frequency. The ADC consumes 150mW at 1.8V supply and achieves a Figure-of-Merit (FoM) of 700fJ/conv-step. References : [1] Alpman, E., Lakdawala, H., Carley, L. R., & Soumyanath, K. (2009, 8-12 Feb. 2009). A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP digital CMOS. Paper presented at the 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers. [2] Choi, M., & Abidi, A. A. (2001, 7-7 Feb. 2001). A 6 b 1.3 GSample/s A/D converter in 0.35 /spl mu/m CMOS. Paper presented at the 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177). [3] Ying-Zu, L., Soon-Jyh, C., Yen-Ting, L., Chun-Cheng, L., & Guang-Ying, H. (2009, 8-12 Feb. 2009). A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS. Paper presented at the 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers. [4] Varonen, M., Kaltiokallio, M., Saari, V., Viitala, O., Karkkainen, M., Lindfors, S., Halonen, K. A. I. (2009, 7-9 June 2009). A 60-GHz CMOS receiver with an on-chip ADC. Paper presented at the 2009 IEEE Radio Frequency Integrated Circuits Symposium. [5] Harpe, P., Cantatore, E., & Roermund, A. v. (2013). A 10b/12b 40 kS/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ/Conversion-Step. IEEE Journal of Solid-State Circuits, 48(12), 3011-3018. doi: 10.1109/JSSC.2013.2278471 [6] Shikata, A., Sekimoto, R., Kuroda, T., & Ishikuro, H. (2012). A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS. IEEE Journal of Solid-State Circuits, 47(4), 1022-1030. doi: 10.1109/JSSC.2012.2185352

[7] Guerber, J., Venkatram, H., Gande, M., Waters, A., & Moon, U. K. (2012). A 10-b Ternary SAR ADC With Quantization Time Information Utilization. IEEE Journal of Solid-State Circuits, 47(11), 2604-2613. doi: 10.1109/JSSC.2012.2211696 [8] Jin, J., Gao, Y., & Sánchez-Sinencio, E. (2014). An Energy-Efficient Time-Domain Asynchronous 2 b/Step SAR ADC With a Hybrid R-2R/C-3C DAC Structure. IEEE Journal of Solid-State Circuits, 49(6), 1383-1396. doi: 10.1109/JSSC.2014.2317139 [9] Khorami, A., & Sharifkhani, M. (2016). High-speed low-power comparator for analog to digital converters. AEU - International Journal of Electronics and Communications, 70(7), 886894. doi: http://dx.doi.org/10.1016/j.aeue.2016.04.002 [10] Vogel, C., & Kubin, G. (2005). Modeling of time-interleaved ADCs with nonlinear hybrid filter banks. AEU - International Journal of Electronics and Communications, 59(5), 288-296. doi: http://dx.doi.org/10.1016/j.aeue.2005.05.008 [11] AEUE - International Journal of Electronics and Communications [12] Dabbagh-Sadeghipour, K., Hadidi, K., & Khoei, A. (2006). A new successive approximation architecture for high-speed low-power ADCs. AEU - International Journal of Electronics and Communications, 60(3), 217-223. doi: http://dx.doi.org/10.1016/j.aeue.2005.03.006 [13] Talekar, S. G., Ramasamy, S., Lakshminarayanan, G., & Venkataramani, B. (2009, 23-26 Jan. 2009). A low power 700MSPS 4bit time interleaved SAR ADC in 0.18um CMOS. Paper presented at the TENCON 2009 - 2009 IEEE Region 10 Conference. [14] Tabasy, E. Z., Shafik, A., Huang, S., Yang, N. H. W., Hoyos, S., & Palermo, S. (2013). A 6b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS. IEEE Journal of Solid-State Circuits, 48(8), 1885-1897. doi: 10.1109/JSSC.2013.2259036 [15] Yang, J., Naing, T. L., & Brodersen, R. W. (2010). A 1 GS/s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing. IEEE Journal of Solid-State Circuits, 45(8), 1469-1478. doi: 10.1109/JSSC.2010.2048139