S CMOS ADC in 1-MM∗∗2

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Engineering Information Abstracts (Part II)

design of an ADC circuit. The fabricated ADC shows a signal-to-noise ratio ŽSNR. of 43 dB Ž7.3 bits. under a differential clock of 4.9 GHz with a power dissipation of 400 mW. ŽAuthor abstract . 4 Refs. In English EI Order Number: EIP98024080952 Keywords: Analog to digital conversion; Comparator circuits; High electron mobility transistors; Signal to noise ratio; Semiconducting indium compounds; Electron device manufacture Title: MONOLITHIC 4 BIT 2 GSPS RESONANT TUNNELING ANALOG-TO-DIGITAL CONVERTER Author(s): Broekaert, T.P.E.; Brar, B.; van der Wagt, J.P.A.; Seabaugh, A.C. ; Moise, T.S.; Morris, F.J.; Beam, E.A. III; Frazier, G.A. Corporate Source: Texas Instruments Inc, Dallas, TX, USA Conference Title: Proceedings of the 1997 19th Annual GaAs IC Symposium Conference Location: Anaheim, CA, USA Conference Date: 19971012-19971015 Source: IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design, Proceedings 1997. IEEE, Piscataway, NJ, USA,97CH36098. p 187-190 CODEN: 002553 Publication Year: 1997 Abstract: The combination of resonant tunneling diodes ŽRTDs. and heterostructure field-effect transistors ŽHFETs. provides a versatile technology for implementing microwave digital and mixed-signal applications. Here we demonstrate the first monolithic flash RTDrHFET analog-to-digital converter ŽADC.. The first pass ADC achieved 2.7 effective bits at 2 GSps. The one bit quantizer achieved a single tone spurious free dynamic range ŽSFDR. of greater than 40 dB at 2 GSps for a 220 MHz single tone input with dithering. ŽAuthor abstract . 8 Refs. In English EI Order Number: EIP98024080973 Keywords: Analog to digital conversion; Tunnel diodes; Heterojunctions; Field effect transistors Title: 1.9-GHZ WIDE-BAND IF DOUBLE CONVERSION CMOS RECEIVER FOR CORDLESS TELEPHONE APPLICATIONS Author(s): Rudell, Jacques C.; Ou, Jia-Jiunn; Cho, Thomas Byunghak; Chien, George; Brianti, Francesco; Weldon, Jeffrey A.; Gray, Paul R. Corporate Source: Univ of California at Berkeley, Berkeley, CA, USA Source: IEEE Journal of Solid-State Circuits v 32 n 12 Dec 1997. p 2071-2088 CODEN: IJSCBC ISSN: 0018-9200 Publication Year: 1997 Abstract: A monolithic 1.9-GHz, 198-mW, 0.6- mu m CMOS receiver which meets the specifications of the Digital Enhanced Cordless Telecommunications ŽDECT. standard is described. All of the RF, IF, and baseband receiver components, with the exception of the frequency synthesizers, have been integrated into a single chip solution. A description is given of a wide-band IF with double conversion architecture which eliminates the need for the discrete-component noise and IF filters in addition to facilitating the eventual integration of the frequency synthesizer blocks with on-chip VCO’s. The proto-

type device utilizes a 3.3-V supply and includes a low noise amplifier, an image-rejection mixer, and two quadrature baseband signal paths each of which includes a second-order Sallen and Key anti-alias filter, an eighth-order switchedcapacitor filter network followed by a 10-b pipelined analogto-digital converter ŽADC.. The experimental device has a measured receiver reference sensitivity of minus 90 dBm, an input referred IP3 of minus 7 dBm, a Prr minus rr1rr rrarrB of minus 24 dBm, and an image-rejection ratio of minus 55 dBc across the DECT bands. ŽAuthor abstract . 47 Refs. In English EI Order Number: EIP98013999861 Keywords: Radio receivers; Cordless telephones; CMOS integrated circuits; Frequency synthesizers; Variable frequency oscillators; Amplifiers Želectronic.; Mixer circuits; Electric filters; Analog to digital conversion; Standards Title: CASCADED SIGMA-DELTA PIPELINE A r D CONVERTER WITH 1.25 MHZ SIGNAL BANDWIDTH AND 89 DB SNR Author(s): Brooks, Todd L.; Robertson, David H.; Kelly, Daniel F.; Del Muro, Anthony; Harston, Stephen W. Corporate Source: Analog Devices, Wilmington, MA, USA Source: IEEE Journal of Solid-State Circuits v 32 n 12 Dec 1997. p 1896-1906 CODEN: IJSCBC ISSN: 0018-9200 Publication Year: 1997 Abstract: A low-noise multibit sigma-delta analog-to-digital converter ŽADC. architecture suitable for operation at low over-sampling ratios is presented. The ADC architecture uses an efficient high-resolution pipelined quantizer while avoiding loop stability degradation caused by pipeline latency. A 16-b implementation of the architecture, fabricated in a 0.6- mu m CMOS process, cascades a second-order 5-b sigma-delta modulator with a four-stage 12-b pipelined ADC and operates at a low 8X oversampling ratio. Static and dynamic linearity of the integrated ADC are improved through the use of dynamic element matching techniques and the use of bootstrapped and clock-boosted input switches. The ADC operates at a 20 MHz clock rate and dissipates 550 mW with a 5 Vr3 V analogrdigital supply. It achieves an SNR of 89 dB over a 1.25-MHz signal bandwidth and a total harmonic distortion ŽTHD. of minus 98 dB with a 100-kHz input signal. ŽAuthor abstract . 21 Refs. In English EI Order Number: EIP98013999845 Keywords: Analog to digital conversion; Pipeline processing systems; Bandwidth; Signal to noise ratio; CMOS integrated circuits; Modulators; Signal distortion; Delta modulation; Switching circuits; Digital filters r S CMOS ADC IN Title: EMBEDDED 240-MW 10-B 50-MSr 1-MMUU 2 Author(s): Bult, Klaas; Buchwald, Aaron Corporate Source: Broadcom Corp, Irvine, CA, USA Source: IEEE Journal of Solid-State Circuits v 32 n 12 Dec 1997. p 1887-1895 CODEN: IJSCBC ISSN: 0018-9200 Publication Year: 1997 Abstract: A distributed-gain preamplifier uses averaging to improve resolution by 4 b in differential nonlinearity ŽDNL. and 2 b in integral nonlinearity ŽINL. in a flash analog-to-dig-

Engineering Information Abstracts (Part II) ital converter ŽADC.. Fabricated in a 0.5- mu m, triple-metal, single-poly CMOS process, the circuit measures 1.4 mm multiplied by 1.4 mm including a bandgap and a sample-and-hold ŽSH., while the ADC itself occupies 1-mmUU 2. At a conversion rate of 50-MSrs the ADC dissipates 170 mW, the SH dissipates 70 mW, and the untrimmed ADC-plus-SH exhibits 54 dB SrŽN plus D. with a 12-MHz 90% full-scale input. ŽAuthor abstract . 25 Refs. In English EI Order Number: EIP98013999844 Keywords: Analog to digital conversion; CMOS integrated circuits; Amplifiers Želectronic.; Linear integrated circuits; Crosstalk; Signal filtering and prediction; Switching circuits r S CASCADED FOLDING AND Title: 12-B, 60-MSAMPLEr INTERPOLATING ADC Author(s): Vorenkamp, Pieter; Roovers, Raf Corporate Source: Philips Semiconductors, Caen, Fr Source: IEEE Journal of Solid-State Circuits v 32 n 12 Dec 1997. p 1876-1886 CODEN: IJSCBC ISSN: 0018-9200 Publication Year: 1997 Abstract: This paper describes the analysis, design, and experimental results of a 12-b, 60-MSamplers analog-to-digital converter ŽADC.. This ADC is based on a cascaded folding and interpolating architecture. The ADC is optimized for digital telecommunication applications. The cascaded folding and interpolating ADC architecture is introduced, optimizing the overall performance of this converter. The integrated track & hold amplifier enables an SNR greater than 66 dB and a THD less than 72 dB, measured over an analog input signal bandwidth of 70 MHz. The ADC is realized in a 13-GHz, 1- mu m BiCMOS process and measures 7 mmUU 2, while dissipating 300 mW from a single 5.0 V supply. ŽAuthor abstract . 11 Refs. In English EI Order Number: EIP98013999843 Keywords: Analog to digital conversion; Interpolation; Amplifiers Želectronic.; Signal to noise ratio; Signal distortion; Bandwidth; Bipolar integrated circuits; CMOS integrated circuits; Digital communication systems; Optimization r S LOW-SPURIOUS CMOS ADC Title: 15-B, 5-MSAMPLEr Author(s): Kwak, Sung-Ung; Song, Bang-Sup; Bacrania, Kantilal Corporate Source: Univ of Illinois, Urbana, IL, USA Source: IEEE Journal of Solid-State Circuits v 32 n 12 Dec 1997. p 1866-1875 CODEN: IJSCBC ISSN: 0018-9200 Publication Year: 1997 Abstract: A 5-5-5-6-b pipelined analog-to-digital converter ŽADC. architecture alleviates the requirements for initial capacitor matching and residue amplifier settling accuracy. The two 5-b most significant bit ŽMSB. stages are digitally calibrated to implement a 15-b, 5-Msamplers low-spurious ADC using 1.4- mu m CMOS. A skip-and-fill algorithm with nonlinear interpolation also opens up the possibility of calibrating ADC’s in the background synchronously with their normal operation. Interpolation results for the background calibration are compared with the foreground calibration results. The prototype ADC exhibits a differential nonlinearity ŽDNL. of plus 0.75r minus 0.6 least significant bit ŽLSB., an integral

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nonlinearity ŽINL. of plus 1.77r minus 1.58 LSB, and all spurious components are suppressed to below minus 93 dB when sampled at 5 MHz. The chip occupies 27 mmUU 2, and the analog part consumes 60 mW at 5 V. Memory and arithmetic units for calibration are supplied externally in testing. ŽAuthor abstract . 21 Refs. In English EI Order Number: EIP98013999842 Keywords: Analog to digital conversion; CMOS integrated circuits; Pipeline processing systems; Algorithms; Interpolation; Calibration; Data storage equipment; Digital arithmetic; Computer architecture r S 8-BIT ADC SYSTEM Title: 8-GSAr Author(s): Poulton, Ken; Knudsen, Knud L.; Kerley, John; Kang, James; Tani, Jon; Cornish, Eldon; VanGrouw, Michael Corporate Source: Hewlett-Packard Co, USA Conference Title: Proceedings of the 1997 Symposium on VLSI Circuits Conference Location: Kyoto, Jpn Conference Date: 19970612-19970614 Source: IEEE Symposium on VLSI Circuits, Digest of Technical Papers 1997. IEEE, Piscataway, NJ, USA,97CH36115. p 23-24 CODEN: 85PXA5 Publication Year: 1997 Abstract: We report on an analog to digital converter ŽADC. system with 8 bit resolution and a sample rate of 8 GSars. The system is composed of 2 thick-film hybrid substrates, each holding a silicon bipolar ADC chip and a custom CMOS memory chip. Each ADC chip contains two differential track and hold circuits and two folding and interpolating 2 GSars flash digitizers. The custom memory chip accepts data at 2 GSars on each of two input ports, and stores the data in a 256 Kbit SRAM. The ADC system uses time interleaving of 4 paths to reach 8 GSars and combines hardware dither with software calibration techniques to achieve 7.6 effective bits at low frequencies and 5.3 effective bits at 2 GHz input. ŽAuthor abstract . 5 Refs. In English EI Order Number: EIP97113912783 Keywords: Analog to digital conversion; Thick film devices; Semiconducting silicon; CMOS integrated circuits; Random access storage; Semiconductor storage r AREA EFFICIENT 8-BIT A r D AND D r A DETitle: FASTr SIGNS IN 0.8 MU M CMOS TECHNOLOGY USING LAYOUT GENERATORS Author(s): Balakrishnan, Vidya G.; Ramaswamy, Sridhar; Siferd, Raymond E. Corporate Source: Wright State Univ, Dayton, OH, USA Conference Title: Proceedings of the 1997 IEEE National Aerospace and Electronics Conference, NAECON. Part 1 Žof 2. Conference Location: Dayton, OH, USA Conference Date: 19970714-19970717 Source: National Aerospace and Electronics Conference, Proceedings of the IEEE v 1 1997. IEEE, Piscataway, NJ, USA,97CH36015. p 372-377 CODEN: NASEA9 Publication Year: 1997 Abstract: High performance 8-bit analog-to-digital ŽArD. and digital-to-analog ŽDrA. converters are presented here. To