456
W O R L DABSTRACTS ON MICROELECTRONICS
AND RELIABILITY
A software reliability program. O. L. WILLIAMSON,G. G. Dom~IS, A. J. RYBERG and W. E. STRAIGHT,Proc. 1970 Ann. Symp. Reliab., Los Angeles. IEEE Cat. No. 70 C 2-R, 3-5 February (1970), p. 420. This paper presents a framework for the development of a software reliability program suitable for application at the initiation of the planning phase. The development phases, reliability, functional analysis, and error source and effect analyses are discussed in a software context. Also, a software reliability theory and a reliability analysis for a sample software system are presented. In this paper, concepts which have proven useful in evaluating a hardware reliability program are utilized whenever possible.
Failure analysis as a tool for determining semiconductor screens. J. L. LATOUR, Solid St. Technol., March (1970), p. 84. To eliminate failed components prior to use in a system, a screening program must be conducted. For a screening program to be effective the failure modes should be identified. Failure analysis provides an effective method for identifying failure modes and thus aids in choosing the proper screen. S t a n d a r d items form troubleshooter for electronic systems on British jets. Electronics, 27 April (1970), p. 65. Now British Overseas Airways Corp. and Marconi Instruments Ltd. have got together and devised a comprehensive troubleshooter based on the Autotest programed production-checkout gear marketed by M I for the past two years. For a basic cost in the region of $120,000, BOAChas a machine that will pinpoint faults in over 130 circuit boards used in the non-radio-frequency electronics systems in its new Boeing 747 jumbo jets.
4. M I C R O E L E C T R O N I C S - - - G E N E R A L
MOS course--I. The basic structures. E. M. WILDER, Electron. Engr 29, No. 2, February (1970), p. 58. This article, the first in a series on MOS, treats the various structures of the MOS device. Included is a tabulation of parameters for the different types of low-threshold MOS.
Other approaches to integrated circuits. C. DEN BRINKER, Electron. Equip. News, May (1970), p. 36. As change for change's sake is rarely acceptable as a philosophy, one must ask oneself when considering alternative methods of doing things. (a) Does the new method allow me to do things I could not do before? OR (b) Does the new technique allow me to deal more efficiently or effectively with existing problems. In both cases a very strong drive for innovation is provided by the needs of industry. In the immediate future three broad areas will dominate integration developments---switching, linear and microwaves; this will be the format in which possible changes and improvements will be considered.
5. M I C R O E L E C T R O N I C S
DESIGN AND CONSTRUCTION
Hybrid microelectronics m o d u l e s designed using basic thermal design guidelines. A. P. MANDEL, Proc. Tech. Prog. INTER/NEPCON 1969, Brighton, 14-16 October (1969), p. 91. A major consideration in designing microelectronic systems is heat dissipation. Electronic packaging designers in the past did not worry about thermal studies on the electronic module level because sufficient heat transfer was generally supplied on the machine level. Thermal considerations assumed a new significance with the growth of high density, hybrid, microelectronic packages. This importance arises out of the relationship of device performance to temperature. All individual devices in a hybrid electronic package must operate reliably since any failure results in the total failure of the multiple device and electronic functions. Extremely high component and power densities in present monolithic integrated circuits stress the importance of thermal considerations in the total package design. Thermal transfer is likely to be a limiting factor in packaging, requiring not only internal cooling means with accompanying increase in volume and weight, but also special cooling means externally in the form of heat exchangers, through which the heat may be dissipated by conduction, convection and/or radiation. A flip c h i p interconnection and packaging system. J. E. CuaanN and G. GRAVES,Proc. Teeh. Prog. INTER/ NEPCON, Brighton, 14-16 October (1969), p. 103. This paper describes work carried out in the research and development laboratories of the Plessey Company at Poole. It was partly financed as a Ministry of Technology Advanced Computer Techniques Project. They were required to use standard Plessey intergrated circuit chips i.e. Process 1, 11 and MOST devices. T o take full advantage of the speeds at which it was predicted the chip would operate it was necessary to reduce the interconnection lead lengths and circuit capacitance as much as possible. Hence a face down method for chip attachment was decided upon. The work may be considered in seven sections. (1) Description and suitability of interconnection technique. (2) Substrate and metal systems. (3) Fabrication of interconnections. (4) Ultrasonic bonding of chips. (5) Crossover techniques. (6) Thermal dissipation. (7) Packaging of modules.