- Email: [email protected]
The fast microprocessor [32-bit microprocessor Am2900]
two different bus systems are included, one providing the burst mode run. The operational speed of the Z280 is enhanced by the cache memory, and the CPU with the programmable peripheral device on the chip allows the control processes to be carded out. LG.
The fast microprocessor [32-bit microprocessor Am2900] L NACHTMANN Chip (Germany), no. 7, pp. 36-38 (July 1987). In German. The design operates with the three-address RISC architecture using a large set of local and global registers. The local register addressing is carded out through the stack for intermediate storage based on the principle of propagation time-stack-cache memory. In addition, register banking ensures rapid context change. The risk of interferences is minimised with the fourstage pipelining, while speed of the process is enhanced with the virtual storage and with the arithmetic unit-
I.G.
56
A BiCMOS image signal processor ~ith line memories Y KOBAYASHI, T FUKUSHIMA, S MIURA, M KANASAKI, K HIRASAWA (Hitachi Res. Lab., Ibaraki, Japan), K ASADA, J IDE,4~'YAMASAKI, Y TANIHARA 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25-27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 182183, 392 The processor has been designed to perform twodimensional basic image processing, but with t~'o updated modifications. To achieve real-time processing of up to 512 • 512 pixel noninterlaced TV images, the processor has been fabricated by a 1.8 lam BiCMOS process to provide a 25 MHz/pixel operating frequency. Additionally, the device has a stand-alone capability as a one-chip image processor. Two line memories have been integrated on the chip and a time division method is implemented. As a result, spatial image operations such as a 3 • 3 spatial convolution can be carded out without additional circuitry. (2 refs.)
The fast microprocessor [32-bit microprocessor Am2900] L NACHTMANN Chip (Germany), no. 7, pp. 36-38 (July 1987). In German. The design operates with the three-address RISC architecture using a large set of local and global registers. The local register addressing is carded out through the stack for intermediate storage based on the principle of propagation time-stack-cache memory. In addition, register banking ensures rapid context change. The risk of interferences is minimised with the fourstage pipelining, while speed of the process is enhanced with the virtual storage and with the arithmetic unit-
I.G.
56
A BiCMOS image signal processor ~ith line memories Y KOBAYASHI, T FUKUSHIMA, S MIURA, M KANASAKI, K HIRASAWA (Hitachi Res. Lab., Ibaraki, Japan), K ASADA, J IDE,4~'YAMASAKI, Y TANIHARA 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25-27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp. 182183, 392 The processor has been designed to perform twodimensional basic image processing, but with t~'o updated modifications. To achieve real-time processing of up to 512 • 512 pixel noninterlaced TV images, the processor has been fabricated by a 1.8 lam BiCMOS process to provide a 25 MHz/pixel operating frequency. Additionally, the device has a stand-alone capability as a one-chip image processor. Two line memories have been integrated on the chip and a time division method is implemented. As a result, spatial image operations such as a 3 • 3 spatial convolution can be carded out without additional circuitry. (2 refs.)